AI-Driven RTL Architect for On-Chip Interconnect

Kindredventures; Palo Alto (CA); On-site; USD 190,000 - 260,000; Full time

Job summary

Architect, a frontier AI lab for chip design, seeks a Founding Member of the Technical Staff to own the AI‑driven RTL design of interconnect fabrics and NoC routers for production silicon.

You will define block-level microarchitectures, specify interfaces, and lead collaboration with DV, SW, and ML teams to optimize latency, bandwidth, and power while enabling FPGA prototyping for early validation.

Qualifications

• Bachelor’s/Master’s/PhD in EE/CE or related field.
• 5+ years RTL design experience; 10+ preferred; tapeout interconnect experience.
• Deep AMBA protocol knowledge (AXI/AXI5/ACE/CHI) and NoC/fabric design experience.

Responsibilities

• Own the on-chip fabric RTL end-to-end, from NoC topology to timing closure.
• Design AMBA-based interconnect fabrics and bridges (AXI/ACE/CHI).
• Architect NoC routers and topologies with QoS and deadlock-free design.
• Build RTL infrastructure and AI-driven flow, including scripts and regression.
• Collaborate with the principal architect to refine microarchitectural specs and trade-offs.
• Define and maintain interface specifications (AXI4/AXI5, ACE, CHI, AXI-Stream).
• Support FPGA prototyping on Xilinx for early validation.
• Collaborate with DV, SW, and ML to optimize interconnect performance.

Skills

RTL design

SystemVerilog

AMBA protocol expertise

NoC/fabric design

High-speed I/O integration

Python

Synthesis & timing closure

QoS & deadlock-free design

Education

Bachelor’s/Master’s/PhD in Electrical or Computer Engineering

Tools

Xilinx Vivado/Vitis

Job description

Architect, a frontier AI lab for chip design, seeks a Founding Member of the Technical Staff to own the AI‑driven RTL design of interconnect fabrics and NoC routers for production silicon.

You will define block-level microarchitectures, specify interfaces, and lead collaboration with DV, SW, and ML teams to optimize latency, bandwidth, and power while enabling FPGA prototyping for early validation.