AI-Driven Chip Verification Methodology Engineer

TenX Semi; San Francisco (CA); Hybrid; USD 150,000 - 190,000; Full time

Job summary

TenX Semi is seeking a Chip Design and Verification Methodology Engineer in the San Francisco Bay Area. You will develop innovative methodologies to design and verify chip designs, focusing on AI-generated RTL verification and maximal automation.

You will architect verification loops, establish reusable test environments, and build convergence monitoring, deep-dive debugging tools, and formal proof generation to ensure robust, trustworthy chip designs.

Qualifications

• Fluency in Verilog and SystemVerilog for design and verification TBs.
• Strong experience with SystemVerilog Assertions for complex protocols.
• Deep experience with UVM including constrained-random verification and coverage.
• Solid understanding of pipelines, FSMs, clock domain crossing, and memory hierarchy.
• Ability to read and analyze waveforms to root cause issues and feed AI models.

Responsibilities

• Drive Verification Methodology and Environment for AI-generated RTL with high automation.
• Architect test environments that scale across customer designs and integrate simulation, formal, and emulation.
• Build convergence monitoring to measure coverage and define when AI-generated designs are complete.
• Develop tools to parse and analyze waveforms and trace signal dependencies for root causes.
• Collaborate with AI engineers to ensure verification feedback improves model accuracy.
• Produce formal proofs for critical paths ensuring safety-critical properties hold.

Skills

Verilog/SystemVerilog

SystemVerilog Assertions

UVM

Computer Architecture

Waveform Analysis

Automation / Python

Education

MS/PhD in Electrical Engineering or Computer Science

Tools

Verdi/SIMVision/DVE

JasperGold or VC Formal

Job description

TenX Semi is seeking a Chip Design and Verification Methodology Engineer in the San Francisco Bay Area. You will develop innovative methodologies to design and verify chip designs, focusing on AI-generated RTL verification and maximal automation.

You will architect verification loops, establish reusable test environments, and build convergence monitoring, deep-dive debugging tools, and formal proof generation to ensure robust, trustworthy chip designs.