AI Accelerator RTL Microarchitecture Engineer

RosaicLabs Inc; Santa Clara (CA); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical (including HSA plans)

Dental

Vision

Employee Life & AD&D

401(k)

Job summary

RosaicLabs Inc is seeking a skilled ASIC design engineer to own the design and implementation of functional blocks within the accelerator pipeline in our Santa Clara campus. You will write and debug RTL (Verilog/SystemVerilog) for your assigned block and collaborate with verification engineers to define test plans and close coverage.

The role requires hands-on experience with modern ISA concepts, timing and power closure, and a solid understanding of end-to-end ASIC design flow.

Qualifications

• BS/MS in Electrical/Computer Engineering or related field.
• Coursework in computer microarchitecture.
• Hands-on Verilog/SystemVerilog experience.
• Familiarity with parallel accelerator architectures (e.g. SIMD/SIMT).
• Understanding of end-to-end ASIC design flow and VLSI concepts.
• Scripting experience (Python, Perl, or Tcl).

Responsibilities

• Own the design and implementation of functional blocks within the accelerator pipeline.
• Write and debug RTL (Verilog/SystemVerilog) for your assigned block.
• Collaborate with verification engineers to define test plans and close coverage.
• Analyze performance, timing, and area tradeoffs and propose improvements.
• Participate in design reviews and document your block's architecture and behavior.

Skills

RTL Design

Verilog/SystemVerilog

Performance analysis

Test plan development

Scripting (Python, Perl, Tcl)

C/C++ knowledge

Education

BS/MS in Electrical/Computer Engineering or related field

Tools

Verilog/SystemVerilog simulators

ASIC design flow tools

Job description

RosaicLabs Inc is seeking a skilled ASIC design engineer to own the design and implementation of functional blocks within the accelerator pipeline in our Santa Clara campus. You will write and debug RTL (Verilog/SystemVerilog) for your assigned block and collaborate with verification engineers to define test plans and close coverage.

The role requires hands-on experience with modern ISA concepts, timing and power closure, and a solid understanding of end-to-end ASIC design flow.