AI Accelerator Verification Engineer — RTL to Emulation

RosaicLabs Inc; Austin (TX); On-site; USD 120,000 - 160,000; Full time

Benefits offered by this job

Medical (including HSA)

Dental

Vision

Life & AD&D

401(k)

Job summary

RosaicLabs Inc is seeking an AI Accelerator Design Verification Engineer to own verification environments for AI chips, from test plans to coverage closure and SI bring-up. You will develop verification plans and write SystemVerilog/UVM testbenches, plus build emulation-friendly benches for sim and FPGA prototypes.

You will verify datapaths against bit-accurate models, run ML kernels, and collaborate with RTL/design teams to drive bugs to closure while using formal verification where

Qualifications

• Bachelor's or Master's in Electrical/Computer Engineering, CS or related field.
• Strong background in AI accelerator design and computer architecture.
• Experience with SystemVerilog/UVM and modern verification flows.
• Familiarity with emulation, FPGA prototyping, and coverage concepts.

Responsibilities

• Develop verification plans for AI accelerator blocks and SoC flows.
• Write and debug SystemVerilog/UVM testbenches, checkers, and scoreboards.
• Build emulation-friendly testbenches for sim and emulators/FPGA prototypes.
• Verify compute datapaths against bit-accurate models and run ML kernels.
• Apply formal verification and triage regression failures across platforms.

Skills

SystemVerilog/UVM

C/C++

Python scripting

RTL debugging

Emulation/FPGA

SVA

AI accelerator basics

Education

Bachelor's or Master's in Electrical/Computer Engineering or CS

Tools

SystemVerilog

UVM

Emulation platforms

FPGA prototyping

ISA simulators

Job description

RosaicLabs Inc is seeking an AI Accelerator Design Verification Engineer to own verification environments for AI chips, from test plans to coverage closure and SI bring-up. You will develop verification plans and write SystemVerilog/UVM testbenches, plus build emulation-friendly benches for sim and FPGA prototypes.

You will verify datapaths against bit-accurate models, run ML kernels, and collaborate with RTL/design teams to drive bugs to closure while using formal verification where