CPU RTL & Microarchitecture Engineer

RosaicLabs Inc; Austin (TX); On-site; USD 110,000 - 170,000; Full time

Benefits offered by this job

Medical (incl. HSA)

Dental

Vision

Life & AD&D

401(k)

Job summary

RosaicLabs Inc. is seeking an experienced hardware engineer to design and implement CPU functional blocks and optimize RTL using SystemVerilog/Verilog.

You will analyze tradeoffs in performance, timing, and power while collaborating with verification and physical design teams to meet area and timing goals. The role requires a strong understanding of computer architecture, DSP/CPU fundamentals, and hands-on RTL experience, along with scripting skills (Python/Tcl) to support automation and test

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• Strong foundation in computer architecture and digital design with knowledge of key areas.
• Hands-on Verilog/SystemVerilog experience including RTL simulation and testbench debugging.
• Familiarity with the ASIC design flow: RTL design, verification, synthesis, timing analysis.

Responsibilities

• Design and implement CPU functional blocks based on microarchitecture specifications.
• Develop, debug, and optimize RTL using SystemVerilog/Verilog.
• Analyze performance, timing, area, and power tradeoffs and propose improvements.
• Work with verification engineers to develop test plans and achieve functional coverage.
• Partner with physical design engineers on area, timing, and power goals.
• Participate in microarchitecture and RTL design reviews and write technical documentation.

Skills

CPU architecture

Verilog/SystemVerilog

Digital design

Automation scripting

Education

Electrical Engineering

Computer Engineering

Tools

Python

Tcl

C/C++

Job description

RosaicLabs Inc. is seeking an experienced hardware engineer to design and implement CPU functional blocks and optimize RTL using SystemVerilog/Verilog.

You will analyze tradeoffs in performance, timing, and power while collaborating with verification and physical design teams to meet area and timing goals. The role requires a strong understanding of computer architecture, DSP/CPU fundamentals, and hands-on RTL experience, along with scripting skills (Python/Tcl) to support automation and test