Hands-On CPU RTL Microarchitecture Engineer

RosaicLabs Inc; Santa Clara (CA); On-site; USD 120,000 - 170,000; Full time

Job summary

RosaicLabs Inc. in Santa Clara, CA is seeking a CPU design engineer to design and implement CPU functional blocks, and optimize RTL in SystemVerilog. You will work with verification and physical design teams to ensure performance and power goals.

The role requires strong knowledge of computer architecture, digital design, and hands-on RTL experience with Verilog/SystemVerilog, plus scripting for automation. Bachelor's or Master's in EE/CE/CS are expected.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• Strong foundation in computer architecture and digital design with knowledge in at least two areas: out-of-order execution, CPU front-end/control logic, memory systems, cache coherency, virtual memory, floating-point, SIMD.
• Hands-on Verilog/SystemVerilog experience including RTL simulation and testbench-based debugging.
• Familiarity with ASIC design flow: RTL design, verification, synthesis, timing analysis.
• Scripting experience for automation or data analysis (Python, Perl, Tcl, or C/C++).

Responsibilities

• Design and implement CPU functional blocks based on microarchitecture specifications.
• Develop, debug, and optimize RTL using SystemVerilog/Verilog.
• Analyze performance, timing, area, and power tradeoffs and propose improvements.
• Work with verification engineers to develop test plans and achieve functional coverage.
• Partner with physical design engineers on area, timing, and power goals.
• Participate in microarchitecture and RTL design reviews and write technical documentation.

Skills

CPU architecture

RTL design

Verilog/SystemVerilog

ASIC flow knowledge

Python scripting

Testbench debugging

Education

Bachelor's or Master's in EE/CE/CS

Tools

SystemVerilog

Job description

RosaicLabs Inc. in Santa Clara, CA is seeking a CPU design engineer to design and implement CPU functional blocks, and optimize RTL in SystemVerilog. You will work with verification and physical design teams to ensure performance and power goals.

The role requires strong knowledge of computer architecture, digital design, and hands-on RTL experience with Verilog/SystemVerilog, plus scripting for automation. Bachelor's or Master's in EE/CE/CS are expected.