AI Accelerator RTL Microarchitecture/Design Engineer - Full Time

RosaicLabs Inc; Santa Clara (CA); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical (including HSA plans)

Dental

Vision

Employee Life & AD&D

401(k)

Job summary

RosaicLabs Inc is seeking a skilled ASIC design engineer to own the design and implementation of functional blocks within the accelerator pipeline in our Santa Clara campus. You will write and debug RTL (Verilog/SystemVerilog) for your assigned block and collaborate with verification engineers to define test plans and close coverage.

The role requires hands-on experience with modern ISA concepts, timing and power closure, and a solid understanding of end-to-end ASIC design flow.

Qualifications

• BS/MS in Electrical/Computer Engineering or related field.
• Coursework in computer microarchitecture.
• Hands-on Verilog/SystemVerilog experience.
• Familiarity with parallel accelerator architectures (e.g. SIMD/SIMT).
• Understanding of end-to-end ASIC design flow and VLSI concepts.
• Scripting experience (Python, Perl, or Tcl).

Responsibilities

• Own the design and implementation of functional blocks within the accelerator pipeline.
• Write and debug RTL (Verilog/SystemVerilog) for your assigned block.
• Collaborate with verification engineers to define test plans and close coverage.
• Analyze performance, timing, and area tradeoffs and propose improvements.
• Participate in design reviews and document your block's architecture and behavior.

Skills

RTL Design

Verilog/SystemVerilog

Performance analysis

Test plan development

Scripting (Python, Perl, Tcl)

C/C++ knowledge

Education

BS/MS in Electrical/Computer Engineering or related field

Tools

Verilog/SystemVerilog simulators

ASIC design flow tools

Job description

• Own the design and implementation of functional blocks within the accelerator pipeline
• Write and debug RTL (Verilog/SystemVerilog) for your assigned block
• Collaborate with verification engineers to define test plans and close coverage
• Analyze performance, timing, and area tradeoffs and propose improvements
• Participate in design reviews and document your block's architecture and behavior

What you'll do

• Own the design and implementation of functional blocks within the accelerator pipeline
• Write and debug RTL (Verilog/SystemVerilog) for your assigned block
• Collaborate with verification engineers to define test plans and close coverage
• Analyze performance, timing, and area tradeoffs and propose improvements
• Participate in design reviews and document your block's architecture and behavior

What we're looking for

• BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field
• Recently completed coursework in computer microarchitecture, covering at least one of:

• Cache/memory systems
• Computer arithmetic
• Pipeline design

• Working knowledge of a modern ISA

• Familiarity with parallel accelerator architectures, such as:

• SIMD / SIMT / vector processing
• Out-of-order scheduling

• Hands-on Verilog/SystemVerilog experience, including:

• Simulation and testbench debugging
• Timing and power closure

• Understanding of the end-to-end ASIC design flow and general VLSI concepts

• Scripting experience (Python, Perl, or Tcl); C/C++ a plus

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

Benefits:

• Medical (including HSA plans)
• Dental
• Vision
• Employee Life & AD&D
• 401(k)