AI Accelerator Verification Engineer — Build Next‑Gen AI Chips

RosaicLabs; Santa Clara (CA); On-site; USD 125,000 - 250,000; Full time

Benefits offered by this job

Medical

Dental

Vision

Employee Life & AD&D

401(k)

Job summary

RosaicLabs in Santa Clara, CA seeks an AI Accelerator Design verification engineer to own verification environments from test plans through coverage closure and SI bring-up. You will develop verification plans for AI accelerator blocks, write SystemVerilog/UVM testbenches, and build emulation-friendly environments for testing on emulators or FPGA prototypes.

The role requires a strong foundation in AI accelerator architectures, tensor cores, and on‑chip memories, with scripting in

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science or a related field.
• Proficiency in SystemVerilog, C/C++, and assembly for verification environments.
• Experience with AI accelerator concepts, tensor cores, and on‑chip memories.

Responsibilities

• Develop verification plans for AI accelerator blocks: tensor processing, fabric / network-on-chip, and SoC flows.
• Write and debug SystemVerilog/UVM testbenches, checkers, stimulus, scoreboards, and reference models.
• Build emulation-friendly testbenches and run tests on emulation/FPGA prototypes.
• Use agentic AI tools across the verification workflow and review generated results.
• Verify numerical correctness of compute datapaths against bit-accurate models.
• Run ML kernels and randomized programs on RTL co-simulated with reference models.
• Define, implement, and close functional and code coverage goals to drive closure.
• Debug failures across RTL, testbenches, and reference models with RTL designers.
• Apply formal verification, assertions (SVA), and emulation to improve quality.

Skills

SystemVerilog

C/C++

assembly

Python

Tcl

Rust

SVA

emulation

AI tools

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science or a related field

Job description

RosaicLabs in Santa Clara, CA seeks an AI Accelerator Design verification engineer to own verification environments from test plans through coverage closure and SI bring-up. You will develop verification plans for AI accelerator blocks, write SystemVerilog/UVM testbenches, and build emulation-friendly environments for testing on emulators or FPGA prototypes.

The role requires a strong foundation in AI accelerator architectures, tensor cores, and on‑chip memories, with scripting in