AI Accelerator Verification Engineer - Intern/Co-op

RosaicLabs Inc; Santa Clara (CA); On-site; USD 28,000 - 41,000; Part time

Job summary

RosaicLabs Inc in Santa Clara, CA is seeking a student intern or co-op to verify accelerator designs, owning verification environments from test plan through coverage closure. You'll gain hands-on experience with chip design and verification in a collaborative hardware team.

You will write SystemVerilog/UVM testbenches, build scoreboards, triage failures with mentors, and contribute to reviews and documentation of your verification results.

Qualifications

• Pursuing BS/MS in Electrical/Computer Engineering, CS or related field.
• Familiarity with digital design and verification concepts.
• Hands-on SystemVerilog experience including testbench development (UVM preferred).
• Understanding of end-to-end ASIC design flow and VLSI concepts.

Responsibilities

• Develop verification plans for the accelerator with a mentor.
• Write and debug SystemVerilog/UVM testbenches, checkers, and stimulus.
• Build tests, scoreboards, and reference models; close coverage.
• Triage and root-cause failures with RTL designers with mentorship.
• Participate in design and verification reviews and document results.

Skills

SystemVerilog

UVM

Scripting (Python, Perl, Tcl)

Education

BS/MS in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Python

Perl

Tcl

Job description

RosaicLabs Inc in Santa Clara, CA is seeking a student intern or co-op to verify accelerator designs, owning verification environments from test plan through coverage closure. You'll gain hands-on experience with chip design and verification in a collaborative hardware team.

You will write SystemVerilog/UVM testbenches, build scoreboards, triage failures with mentors, and contribute to reviews and documentation of your verification results.