Advanced Packaging Research Engineer - Chiplets & 3DIC

Intel; Phoenix (AZ); On-site; USD 110,000 - 160,000; Full time

Benefits offered by this job

IP/Patents opportunities

Job summary

Intel is seeking a Semiconductor Packaging Research Engineer to drive technology research for advanced packaging and heterogeneous integration. Candidates will evaluate new architectures, materials, interconnects, reliability risks, and manufacturability trade-offs for future products.

The role covers chiplets, 2.5D/3DIC, hybrid bonding, and die-to-die interconnects, with emphasis on either process integration or modeling.

Qualifications

• Master's or Ph.D. in Mechanical Engineering, Electrical Engineering, Materials Science, Applied Physics, Computational Mechanics, Microelectronics, Semiconductor Manufacturing, or related field.
• 1+ years' experience in semiconductor packaging research, advanced packaging integration, process integration, modeling/simulation, reliability, materials, or heterogeneous integration.
• 1+ year of experience with process integration, DOE, defect/yield learning, reliability, model development & validation, or multi-physics simulation.
• 1+ year of experience with advanced packaging technologies such as flip chip, chiplets, 2.5D/3DIC, fan-out, hybrid bonding, interposers, HBM integration.

Responsibilities

• Research advanced packaging concepts such as chiplets, heterogeneous integration, 2.5D/3DIC, hybrid bonding, interposer, and die-to-die interconnects.
• Drive process integration learning or modeling/simulation to assess feasibility, reliability, manufacturability, and TRL.
• For process integration: define integration flows, research vehicles, DOE, defect/yield learning, qualification evidence, and risk mitigation paths.
• For modeling: develop and validate thermal, thermo-mechanical, electrical, reliability, or multi-physics models using experimental data.
• Translate product needs into research hypotheses, technical plans, and recommendations; document outputs through reports, IP, publications, and development-transfer inputs.
• Collaborate across research, design, process, materials, reliability, manufacturing, supplier, university, and ecosystem teams.

Skills

Packaging research

Modeling/simulation

DOE

Reliability assessment

Cross-functional collaboration

Education

Master's or Ph.D. in Mechanical Engineering or related

Tools

ANSYS

Abaqus

COMSOL

HFSS

Cadence

MATLAB

Python

JMP

Job description

Intel is seeking a Semiconductor Packaging Research Engineer to drive technology research for advanced packaging and heterogeneous integration. Candidates will evaluate new architectures, materials, interconnects, reliability risks, and manufacturability trade-offs for future products.

The role covers chiplets, 2.5D/3DIC, hybrid bonding, and die-to-die interconnects, with emphasis on either process integration or modeling.