Head of Advanced Packaging Research & Integration

Intel Corporation; Chandler (AZ); Hybrid; USD 221,000 - 312,000; Full time

Job summary

Intel Corporation is seeking a Semiconductor Packaging Integration Research Manager in the United States (Arizona, Phoenix area) to lead advanced packaging integration research for next‑generation heterogeneous semiconductor technology.

The role drives early‑stage integration strategies, architecture trade‑offs, and feasibility demonstrations while collaborating with device, process, materials, reliability, modeling, test, and manufacturing teams.

Qualifications

• Experience leading advanced technology research programs with multidisciplinary teams or external collaborations.
• Strong understanding of package-system integration, chiplet architectures, and interconnects.
• Ability to translate system requirements into feasible integration solutions and roadmaps.

Responsibilities

• Lead packaging integration research programs focused on heterogeneous integration and 2.5D/3DIC concepts.
• Define research strategy, milestones, and criteria aligned to product, platform, and system scaling needs.
• Manage multidisciplinary teams across packaging technology, modeling, and design.
• Translate system requirements into package integration solutions balancing performance, power, area, and reliability.
• Partner with design, process, materials, reliability, and manufacturing teams to close cross-domain gaps.
• Drive feasibility studies, architecture trade-offs, prototypes, and technology readiness assessments.

Skills

Packaging integration

Chiplet architectures

Research program leadership

Cross-functional collaboration

Executive communication

Education

Master’s degree in engineering

Ph.D. preferred

Job description

Intel Corporation is seeking a Semiconductor Packaging Integration Research Manager in the United States (Arizona, Phoenix area) to lead advanced packaging integration research for next‑generation heterogeneous semiconductor technology.

The role drives early‑stage integration strategies, architecture trade‑offs, and feasibility demonstrations while collaborating with device, process, materials, reliability, modeling, test, and manufacturing teams.