Semiconductor Packaging Research Engineer

Intel; Phoenix (AZ); On-site; USD 110,000 - 160,000; Full time

Benefits offered by this job

IP/Patents opportunities

Job summary

Intel is seeking a Semiconductor Packaging Research Engineer to drive technology research for advanced packaging and heterogeneous integration. Candidates will evaluate new architectures, materials, interconnects, reliability risks, and manufacturability trade-offs for future products.

The role covers chiplets, 2.5D/3DIC, hybrid bonding, and die-to-die interconnects, with emphasis on either process integration or modeling.

Qualifications

• Master's or Ph.D. in Mechanical Engineering, Electrical Engineering, Materials Science, Applied Physics, Computational Mechanics, Microelectronics, Semiconductor Manufacturing, or related field.
• 1+ years' experience in semiconductor packaging research, advanced packaging integration, process integration, modeling/simulation, reliability, materials, or heterogeneous integration.
• 1+ year of experience with process integration, DOE, defect/yield learning, reliability, model development & validation, or multi-physics simulation.
• 1+ year of experience with advanced packaging technologies such as flip chip, chiplets, 2.5D/3DIC, fan-out, hybrid bonding, interposers, HBM integration.

Responsibilities

• Research advanced packaging concepts such as chiplets, heterogeneous integration, 2.5D/3DIC, hybrid bonding, interposer, and die-to-die interconnects.
• Drive process integration learning or modeling/simulation to assess feasibility, reliability, manufacturability, and TRL.
• For process integration: define integration flows, research vehicles, DOE, defect/yield learning, qualification evidence, and risk mitigation paths.
• For modeling: develop and validate thermal, thermo-mechanical, electrical, reliability, or multi-physics models using experimental data.
• Translate product needs into research hypotheses, technical plans, and recommendations; document outputs through reports, IP, publications, and development-transfer inputs.
• Collaborate across research, design, process, materials, reliability, manufacturing, supplier, university, and ecosystem teams.

Skills

Packaging research

Modeling/simulation

DOE

Reliability assessment

Cross-functional collaboration

Education

Master's or Ph.D. in Mechanical Engineering or related

Tools

ANSYS

Abaqus

COMSOL

HFSS

Cadence

MATLAB

Python

JMP

Job description

Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Want to learn more? Visit our YouTube Channel or the link below.

Life at Intel

Position Summary: The Semiconductor Packaging Research Engineer drives technology research for advanced packaging and heterogeneous integration . The role is suited for candidates with expertise in either packaging process integration or modeling / simulation , with a focus on evaluating new architectures, materials, interconnects, reliability risks, and manufacturability trade-offs for future products .

Key Responsibilities

• Research advanced packaging concepts such as chiplets, heterogeneous integration, 2.5D/3DIC, hybrid bonding, interposer , and die-to-die interconnects.
• Drive either process integration learning or modeling/simulation to assess feasibility, reliability, manufacturability, and technology readiness.
• For process integration: define integration flows, research vehicles, DOE, defect/yield learning, qualification evidence, and risk mitigation paths.
• For modeling: develop and validate thermal, thermo-mechanical, electrical, reliability, or multi-physics models using experimental and failure analysis data.
• Translate product needs into research hypotheses, technical plans, and recommendations; document outputs through reports, design guidance, IP, publications, and development-transfer inputs.
• Collaborate across research, design, process, materials, reliability, manufacturing, supplier, university, and ecosystem teams.

For information on Intel's immigration sponsorship guidelines, please see Intel U.S. Immigration Sponsorship Information

Required Qualifications

• Master's or Ph.D. in Mechanical Engineering, Electrical Engineering, Materials Science, Applied Physics, Computational Mechanics, Microelectronics, Semiconductor Manufacturing, or related field.
• 1+ years ' e xperience in semiconductor packaging research, advanced packaging integration, process integration, modeling/simulation, reliability, materials, or heterogeneous integration.
• 1+ years' experience in one or more of the following area s : process integration, research vehicle execution, DOE, defect/yield learning, reliability, model development & validation , or multi-physics simulation.
• 1+ year s ' experience with advanced packaging technologies such as flip chip , chiplets, 2.5D/3DIC, fan-out, hybrid bonding, interposers, HBM integration, advanced substrates, or die-to-die interconnects.

Preferred Qualifications

• Ph.D. or deep technical specialization in packaging process integration, computational mechanics, thermal sciences, electrical modeling, materials reliability, or microelectronics research and 4+ years of relevant experience.
• Experience with prototype builds, technology readiness assessment, research-to-development transfer, package-system co-optimization, or chip-package-board co-design.
• Modeling tool experience such as ANSYS, Abaqus, COMSOL, HFSS, Cadence, MATLAB, Python, JMP, or equivalent platforms.
• Record of patents, publications, conference presentations, technical reports, methodology development, or competitive technology assessments.
• Ability to turn ambiguous research problems into clear assumptions, experiments, learning milestones, qualification metrics, and actionable recommendations.

Key Competencies

• Advanced packaging research and pathfinding
• Process integration or modeling/simulation expertise
• Heterogeneous integration, chiplet, and advanced substrate knowledge
• DOE, prototype learning, reliability assessment, or model validation
• Technology readiness evaluation and cross-functional communication

Success Measures

• Research outputs identify credible integration options, technology limiters, and trade-offs for future platforms.
• Process integration or modeling results are supported by clear assumptions, evidence, validation data, and documented limitations.
• Prototype, DOE, or simulation learning improves feasibility, reliability, integration robustness, and manufacturability understanding.
• Key risks are identified early with practical mitigation paths and development-transfer recommendations.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Benefits at Intel

Our total rewards package goes above and beyon