Senior Chiplet Packaging Architect (2.5D/3D) – 2nm & Beyond

Rapidus Corporation US; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Health coverage

Dental & Vision

Career growth

Global collaboration

Cutting-edge tech

Job summary

Rapidus Corporation is seeking a Chiplet Package Design Engineer to drive 2.5D/3D heterogeneous packaging for next-generation semiconductor products. Lead architecture and integration efforts across interposers, fan-out, and 3D stacking.

You will collaborate with silicon design, OSAT partners, and fabs, focusing on synthesis and place-and-route stages, signal integrity, power integrity, and thermal analysis, while contributing to roadmap and DFx practices.

Qualifications

• B.S. or M.S. in Electrical/Mechanical/Materials or related field.
• 5+ years in semiconductor package design, especially advanced packaging.
• Hands-on with 2.5D/3D packaging technologies (interposer, TSV, hybrid bonding).
• Strong knowledge of high-speed interfaces and SI/PI.
• Experience with OSAT ecosystem and package manufacturing processes.

Responsibilities

• Lead the design and development of 2.5D/3D package architectures.
• Define and optimize chiplet integration strategies.
• Develop package layout and routing for high-speed interconnects.
• Perform SI/PI and thermal analyses.
• Collaborate with silicon teams on bump/pad design and floorplanning.
• Drive package-substrate co-design including material selection.
• Interface with OSATs and foundries for manufacturability and cost.
• Support DFx and reliability validation; contribute to roadmap and bring-up.

Skills

Chiplet packaging

2.5D/3D packaging

High-speed interfaces

Cross-functional teamwork

Synthesis & PnR

DFx (DFM, DFT, DFA)

OSAT collaboration

Die partitioning & interconnect

Education

B.S. or M.S. in Electrical/Mechanical/Materials or related field

Tools

Cadence Allegro Package Designer

Sigrity

Ansys HFSS

RedHawk-SC Electrothermal

Job description

Rapidus Corporation is seeking a Chiplet Package Design Engineer to drive 2.5D/3D heterogeneous packaging for next-generation semiconductor products. Lead architecture and integration efforts across interposers, fan-out, and 3D stacking.

You will collaborate with silicon design, OSAT partners, and fabs, focusing on synthesis and place-and-route stages, signal integrity, power integrity, and thermal analysis, while contributing to roadmap and DFx practices.