Semiconductor Packaging Integration Research Manager

Intel; Phoenix (AZ); On-site; USD 140,000 - 190,000; Full time

Job summary

Intel is seeking a Semiconductor Packaging Integration Research Manager to lead advanced packaging integration research enabling next-generation heterogeneous semiconductor technology. You will guide early-stage strategies across chiplet assembly, 2.5D/3DIC, and wafer-level packaging, balancing performance, power, area, and manufacturability.

You will manage a multidisciplinary team, partner with design, process, reliability, and manufacturing groups, and drive feasibility studies, architecture

Qualifications

• Experience leading multidisciplinary research programs.
• Ability to translate complex integration challenges into actionable plans and milestones.
• Strong understanding of package-system integration, chiplet architectures, interconnects, substrates and reliability trade-offs.
• Excellent communication to executive and cross-functional teams.

Responsibilities

• Lead packaging integration research programs focused on heterogeneous integration and chiplets.
• Define strategy, roadmaps, milestones, and criteria aligned to product and system scaling.
• Manage a multidisciplinary team of researchers, technologists, engineers, and program leads.
• Translate system requirements into package solutions balancing performance, power, area, latency, and manufacturability.
• Partner with design, process, reliability, and manufacturing teams to close cross-domain gaps.
• Drive feasibility studies, architecture trade-offs, and experimental validation for new concepts.
• Conduct technology readiness assessments and manufacturing feasibility reviews for early options.
• Publish IP, benchmark against competitors, and transfer knowledge internally.
• Define qualification gaps, process control needs, and scaling paths for development transfer.
• Communicate progress, risks, and strategic recommendations to senior leaders.

Skills

Advanced packaging

Chiplet architectures

3DIC integration

Cross-functional leadership

Technical storytelling

Power/thermal modeling

Education

PhD in Electrical Engineering

Tools

Ansys

Cadence

MATLAB

Job description

Job Details

Job Description

About the Team

Foundry Technology Research is responsible for developing the breakthrough technologies that will power future generations of semiconductor manufacturing. The team conducts advanced research in devices, materials, interconnects, patterning, packaging, heterogeneous integration, and system technologies, while partnering closely with technology development, manufacturing, and external research ecosystems. Researchers help translate pioneering concepts into viable semiconductor solutions that influence Intel Foundry's long-term roadmap and future customer offerings.

About the Role

The Semiconductor Packaging Integration Research Manager is responsible for leading advanced packaging integration research to enable next-generation heterogeneous semiconductor technology and systems. This role defines and drives early-stage integration strategies across package architecture, chiplet assembly, substrate/interposer technology, wafer-level and die-level integration reliability, and manufacturability. The manager guides exploratory concepts from research to pathfinding through feasibility demonstration, prototype learning, technology readiness assessment, and transfer to development or manufacturing teams, while partnering closely with device, design, process, materials, reliability, modeling, test, manufacturing, university, supplier, and foundry ecosystem partners.

Key Responsibilities

• Lead packaging integration research programs focused on heterogeneous integration, chiplets, 2.5D/3DIC, hybrid bonding, wafer-level packaging, and emerging die-to-die interconnect technologies.
• Define integration research strategy, technical roadmaps, research milestones, and decision criteria aligned to future product, platform, and system-level scaling requirements.
• Manage multidisciplinary team of integration researchers, packaging technologists, process integration engineers, modeling experts, design, and technical program leads.
• Translate system requirements into package integration solutions by balancing performance, power, area, latency, bandwidth, thermal behavior, mechanical stress, reliability, cost, and manufacturability.
• Partner with silicon design, device, process, substrate, assembly, test, reliability, thermal, signal integrity, power delivery, failure analysis, and manufacturing teams to close cross-domain integration gaps.
• Drive feasibility studies, architecture trade-off analysis, process module evaluation, design rule development, prototyping, design-of-experiments, and experimental validation for new integration concepts.
• Lead technology readiness assessments, integration risk reviews, failure analysis learning cycles, reliability evaluations, and manufacturing feasibility reviews for early-stage packaging options.
• Drive intellectual property, technical publications, competitive benchmarking, and internal knowledge transfer related to advanced packaging integration.
• Guide research-to-development transfer by defining integration requirements, qualification gaps, process control needs, manufacturability risks, cost implications, and scaling paths.
• Communicate technical progress, trade-offs, risks, investment needs, and strategic recommendations to senior technical and business leaders.

Key Competencies

• Si-Package co-optimization across process, integration, electrical, thermal, mechanical, reliability, manufacturability, and cost dimensions
• Advanced packaging integration research leadership and technical vision
• Heterogeneous integration, chiplet, 2.5D/3DIC, hybrid bonding, and emerging interconnect expertise
• Technology pathfinding, roadmap definition, research portfolio management, and research-to-development transfer
• Modeling, simulation, prototyping, experimentation, failure analysis, and data-driven integration learning
• Cross-disciplinary influence across device, design, process, materials, test, reliability, thermal, electrical, and manufacturing teams
• External ecosystem collaboration with universities, consortia, suppliers, and equipment vendors
• Strategic communication, risk framing, and executive-level technical storytelling

Required Skills and Experience

• Demonstrated experience leading advanced technology research programs, multidisciplinary technical teams, cross-functional initiatives, or external research collaborations.
• Ability to convert ambiguous integration challenges into clear hypotheses, experimental plans, measurable milestones, technology readiness criteria, and actionable recommendations.
• Strong understanding of package-system integration, chiplet architectures, advanced interconnects, substrates, interposers, assembly materials, wafer-level processes, thermal-mechanical behavior, power delivery, signal integrity, reliability, and manufacturability trade-offs.
• Strong communication skills with the ability to present complex technical findings, integration trade-offs, risks, and recommendations to executive, technical, and cross-functional audiences.