R&D Engineer Adv Tech Dev (PKE) / Sr. Staff

Broadcom Singapore Pte Ltd; Singapore; On-site; SGD 90,000 - 180,000; Full time

Job summary

Broadcom Singapore Pte Ltd is seeking an experienced packaging engineer to design and validate advanced silicon package solutions (5nm, 3nm, 2nm and beyond). You will collaborate with IC design, system design, and packaging teams to meet CPI/SI/PI and thermal requirements for next-generation products.

The role requires hands-on experience with flip-chip, MCM, and 2.5D packaging, as well as deep CPI knowledge, GD&T, and supplier interfaces.

Qualifications

• Education: BS/MS/PhD in STEM/Material Science/Electrical/Mechanical Engineering.
• Experience: BS +8 years or MS +6 years or PhD +3 years.
• Deep understanding of signal integrity and power integrity concepts.
• Strong authority on Cadence APD for custom substrate design.
• Hands-on expertise of advanced and new assembly processes for flipchip, MCM packages, and 2.5D.
• Good understanding of materials related to Chip Packaging Interaction (CPI).
• Familiarity with wafer BEOL related to CPI (top metal, AP, passivation, UBM, bumping).
• Knowledge of advanced substrate manufacturing/process (SAP/mSAP, PSPI w/ Cu RDL).
• In-depth knowledge of failure analysis techniques on advanced node silicon products with ELK and MiM structures.
• Conceptual knowledge of package cost structure.
• Strong project management, communication and leadership skills.
• Must read/comprehend mechanical drawings (GD&T).
• Broad scope across manufacturing/quality, materials, electrical, thermal, and mechanical.

Responsibilities

• Design custom packages with IC design, system design, and packaging teams.
• Ensure packages meet CPI, SI/PI and thermal requirements for advanced node silicon.
• Research and productize new materials supporting 5nm to 2nm nodes.
• Manage IC packaging activity from concept through high volume production.
• Define assembly BOM, process, and troubleshoot packaging issues.
• Implement and productize new technologies into high-volume manufacturing (HVM).
• Create package design documentation and assembly instructions.
• Coordinate with QA and customers to resolve quality issues.
• Interface with suppliers for new product bring-up, qualification and ramp.
• Collaborate with operations groups and other functions for development and projects.
• Support NPI bring-up, package qualification, and production ramp.

Skills

Signal integrity

Power integrity

Cadence APD

Flip-chip packaging

2.5D/3DIC tech

Materials science

GD&T

Project management

Education

BS/MS/PhD in STEM/Materials/Electrical/Mechanical Engineering

Tools

Cadence APD

ELK

MiM structures

PSPI w/ Cu RDL

Job description

Job Description

Work with business unit marketing and IC design teams to select the optimum package solution on cost, performance, manufacturability, and reliability for new advanced silicon node products (5nm, 3nm, 2nm and beyond)

• Work with IC design, system design, package SI/PI & thermal engineering teams to design custom packages
• Ensure designed packages meet CPI, SI/PI, and stringent thermal requirements (1000sW+) of advanced node cutting edge silicon products
• Research, develop, and productize new materials such as TIM, build-up-film, underfill etc. in support advanced node silicon (5nm & 3/2nm) POR definition
• Manage IC packaging activity from concept through development, qualification and high volume production
• Be a specialist and able to define assembly BOM, process, troubleshoot, support on packaging issues on new advanced technology
• Implement, fine-tune, and productize newly developed technologies into HVM
• Create package design documentation and assembly instructions
• Work close with QA and customers to resolve quality issues
• Interface with packaging assembly and substrate suppliers for new product bring-up, qualification and production ramp
• Interface with other operations functional groups such as product engineering, foundry, test, and QA
• Participate in package technology development and/or other business productivity projects which have broad team impact (e.g. assembly process enhancement, new TIM material development etc.)
• Interface with tier #1 external customers for custom ASIC programs or as needed for development support, quality and/or other issue resolution
• Support NPI bring-up, pkg qual, and sustain support in production + multi-source activities for capacity, cost, & manufacturing flexibility needs

Job Requirements

• Education: BS/MS/PHD in STEM/Material Science/Electrical/Mechanical Engineering
• Experience: BS +8 years of experience or MS +6 years of experience or PhD + 3 years of experience is required
• Deep understanding of signal integrity and power integrity concepts such as characteristic impedance, s-parameters (RL, IL, FEXT/NEXT etc.), power plane impedance profile requirements and optimization etc.
• Strong authority on Cadence APD for custom substrate design
• Hands-on expertise of advanced and new assembly processes for flipchip, MCM packages, and 2.5D for advanced node silicon products (5nm, 3/2nm and beyond)
• Good understanding of materials as related to Chip Packaging Interaction (CPI)
• Familiarity with wafer BEOL as related to CPI (top metal, AP, passivation, UBM, bumping etc.)
• Knowledge of advanced substrate manufacturing/process is a must (e.g. SAP/mSAP, PSPI w/ Cu RDL etc.)
• In depth knowledge of failure analysis techniques on advanced node silicon (5nm, 3/2nm etc.) products with ELK and MiM structures
• Conceptual knowledge of package cost structure
• Strong project management, communication and leadership skills
• Must have knowledge of GD&T and be able to read/comprehend mechanical drawings
• Good understanding of manufacturing and quality engineering fundamentals (DOE, process capability indices, etc.)
• Job requirements are broad; the candidate must be able to expand and grow in multiple disciplines (manufacturing/quality, materials, electrical, thermal, and mechanical)
• Track record of innovation and subject matter expertise through journal publications and/or patent awards is desired
• Familiarity with advanced technologies such as 2.5D, 3DIC, glass substrate etc.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.