Senior Packaging R&D Engineer – Advanced Node Solutions

Broadcom Singapore Pte Ltd; Singapore; On-site; SGD 90,000 - 180,000; Full time

Job summary

Broadcom Singapore Pte Ltd is seeking an experienced packaging engineer to design and validate advanced silicon package solutions (5nm, 3nm, 2nm and beyond). You will collaborate with IC design, system design, and packaging teams to meet CPI/SI/PI and thermal requirements for next-generation products.

The role requires hands-on experience with flip-chip, MCM, and 2.5D packaging, as well as deep CPI knowledge, GD&T, and supplier interfaces.

Qualifications

• Education: BS/MS/PhD in STEM/Material Science/Electrical/Mechanical Engineering.
• Experience: BS +8 years or MS +6 years or PhD +3 years.
• Deep understanding of signal integrity and power integrity concepts.
• Strong authority on Cadence APD for custom substrate design.
• Hands-on expertise of advanced and new assembly processes for flipchip, MCM packages, and 2.5D.
• Good understanding of materials related to Chip Packaging Interaction (CPI).
• Familiarity with wafer BEOL related to CPI (top metal, AP, passivation, UBM, bumping).
• Knowledge of advanced substrate manufacturing/process (SAP/mSAP, PSPI w/ Cu RDL).
• In-depth knowledge of failure analysis techniques on advanced node silicon products with ELK and MiM structures.
• Conceptual knowledge of package cost structure.
• Strong project management, communication and leadership skills.
• Must read/comprehend mechanical drawings (GD&T).
• Broad scope across manufacturing/quality, materials, electrical, thermal, and mechanical.

Responsibilities

• Design custom packages with IC design, system design, and packaging teams.
• Ensure packages meet CPI, SI/PI and thermal requirements for advanced node silicon.
• Research and productize new materials supporting 5nm to 2nm nodes.
• Manage IC packaging activity from concept through high volume production.
• Define assembly BOM, process, and troubleshoot packaging issues.
• Implement and productize new technologies into high-volume manufacturing (HVM).
• Create package design documentation and assembly instructions.
• Coordinate with QA and customers to resolve quality issues.
• Interface with suppliers for new product bring-up, qualification and ramp.
• Collaborate with operations groups and other functions for development and projects.
• Support NPI bring-up, package qualification, and production ramp.

Skills

Signal integrity

Power integrity

Cadence APD

Flip-chip packaging

2.5D/3DIC tech

Materials science

GD&T

Project management

Education

BS/MS/PhD in STEM/Materials/Electrical/Mechanical Engineering

Tools

Cadence APD

ELK

MiM structures

PSPI w/ Cu RDL

Job description

Broadcom Singapore Pte Ltd is seeking an experienced packaging engineer to design and validate advanced silicon package solutions (5nm, 3nm, 2nm and beyond). You will collaborate with IC design, system design, and packaging teams to meet CPI/SI/PI and thermal requirements for next-generation products.

The role requires hands-on experience with flip-chip, MCM, and 2.5D packaging, as well as deep CPI knowledge, GD&T, and supplier interfaces.