Package Design Engineer

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Broadcom is seeking an experienced package design engineer for complex flip‑chip‑BGA packages used in AI, networking, HPC, and 5G base stations. You will lead high-frequency structures, ensure SI/PI, and collaborate with a global R&D team across multiple projects.

The role requires 5+ years in flip‑chip‑BGA design (or 3+ for M.Eng) and proficiency with SI/PI concepts and Cadence APD. Strong organizational skills are essential for multi-project execution.

Qualifications

• B.Eng (EE/EEE) or similar field with 5+ years’ experience in flip‑chip‑BGA package design, including high-speed SerDes
• M.Eng (EE/EEE) or similar field with 3+ years’ experience in flip‑chip‑BGA package design, including high-speed SerDes
• Knowledge of package‑level signal integrity and power integrity to apply to package designs
• Cadence APD (Allegro package designer) experience is preferred. Equivalent tools will also be considered.
• Cooperate with our world‑wide team (multiple time zones), including co‑design with internal team members and external (Vendor) designers.
• Good organizational and task management skills to manage multiple package design projects.

Responsibilities

• Overall design responsibility for ASIC package designs (layout/routing), including aspects of impedance matching, crosstalk, signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts.
• Package Design of critical high frequency/datarate structures for SerDes, ADC/DAC, DDR, HBM, etc.
• Schedule, prioritize, & track your work across multiple projects simultaneously
• General flip-chip BGA package design & engineering

Skills

High-speed SerDes

Multinational collaboration

Organizational skills

Education

B.Eng (EE/EEE) or similar field

M.Eng (EE/EEE) or similar field

Tools

Cadence APD (Allegro package designer)

Job description

Broadcom is seeking an experienced package design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and RF/microwave communications A/D-D/A converters (ADC & DAC). You will be part of a worldwide R&D team developing high-performance package designs for ASICs used in artificial intelligence (AI), networking, high-performance computing (HPC), and 5G base stations. These designs include SerDes at 200G and higher, RF/Microwave ADC/DAC, DDR, HBM, and more. You'll have the opportunity to collaborate with the team to create the package structures needed to enable new design.

RESPONSIBILITIES

• Overall design responsibility for ASIC package designs (layout/routing), including aspects of impedance matching, crosstalk, signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts.

• Package Design of critical high frequency/datarate structures for SerDes, ADC/DAC, DDR, HBM, etc.

• Schedule, prioritize, & track your work across multiple projects simultaneously

• General flip-chip BGA package design & engineering

EDUCATION/EXPERIENCE & REQUIREMENTS

• B.Eng (EE/EEE) or similar field and 5+ years’ experience in flip‑chip‑BGA package design, including high-speed SerDes

• M.Eng (EE/EEE) or similar field and 3+ years’ experience in flip‑chip‑BGA package design, including high-speed SerDes

• Knowledge of package‑level signal integrity and power integrity, to apply to package designs

• Cadence APD (allegro package designer) experience is preferred. Equivalent tools will also be considered.

• Cooperate with our world‑wide team (multiple time zones), including co‑design with internal team members and external (Vendor) designers.

• Good organizational and task management skills to manage multiple package design projects.

PREFERRED EDUCATION/EXPERIENCE & REQUIREMENTS

• B.Eng (EE/EEE) or similar field and 8+ years’ experience in flip‑chip‑BGA package design, including high-speed SerDes preferred.

• M.Eng (EE/EEE) or similar field and 6+ years’ experience in flip‑chip‑BGA package design, including high‑speed SerDes preferred.

• Experience with 2.5D and 3DIC packages is highly advantageous.