Package Design Engineer

Avago Technologies Intl' Sales Pte Ltd; Singapore; On-site; SGD 90,000 - 180,000; Full time

Job summary

Broadcom is seeking an experienced package design engineer for complex flip-chip-BGA packages used in high-performance ASICs, with SerDes at 200G and above and RF/microwave ADC/DAC technologies. You will join a global R&D team developing package designs for AI, networking, HPC, and 5G base stations.

Responsibilities include overall design and routing, impedance matching, and ensuring signal/power integrity across multiple projects, with collaboration across internal teams and external vendors.

Qualifications

• B.Eng in EE/EEE with 5+ years in flip-chip-BGA package design including high-speed SerDes.
• M.Eng in EE/EEE with 3+ years in flip-chip-BGA package design including high-speed SerDes.
• Knowledge of package-level signal integrity and power integrity.
• Cadence APD experience preferred; equivalent tools considered.
• Collaborate with worldwide team across multiple time zones.
• Strong organizational and project-management skills.

Responsibilities

• Overall design responsibility for ASIC package designs (layout/routing) including impedance matching, crosstalk, signal integrity, power integrity, manufacturability, reliability, and thermal.
• Package design of high-frequency/high-data-rate structures for SerDes, ADC/DAC, DDR, HBM, etc.
• Schedule, prioritize, and track work across multiple projects.
• General flip-chip BGA package design and engineering.

Skills

High-speed SerDes

Signal integrity

Power integrity

Project coordination

Education

B.Eng in EE/EEE

M.Eng in EE/EEE

Tools

Cadence APD

Allegro

Job description

Broadcom is seeking an experienced package design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and RF/microwave communications A/D-D/A converters (ADC & DAC). You will be part of a worldwide R&D team developing high-performance package designs for ASICs used in artificial intelligence (AI), networking, high-performance computing (HPC), and 5G base stations. These designs include SerDes at 200G and higher, RF/Microwave ADC/DAC, DDR, HBM, and more. You'll have the opportunity to collaborate with the team to create the package structures needed to enable new design.

RESPONSIBILITIES:

• Overall design responsibility for ASIC package designs (layout/routing), including aspects of impedance matching, crosstalk, signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts.
• Package Design of critical high frequency/datarate structures for SerDes, ADC/DAC, DDR, HBM, etc.
• Schedule, prioritize, & track your work across multiple projects simultaneously
• General flip-chip BGA package design & engineering

EDUCATION/EXPERIENCE & REQUIREMENTS:

• B.Eng (EE/EEE) or similar field and 5+ years’ experience in flip-chip-BGA package design, including high-speed SerDes
• M.Eng (EE/EEE) or similar field and 3+ years’ experience in flip-chip-BGA package design, including high-speed SerDes
• Knowledge of package-level signal integrity and power integrity, to apply to package designs
• Cadence APD (allegro package designer) experience is preferred. Equivalent tools will also be considered.
• Cooperate with our world-wide team (multiple time zones), including co-design with internal team members and external (Vendor) designers.
• Good organizational and task management skills to manage multiple package design projects.

PREFERRED EDUCATION/EXPERIENCE & REQUIREMENTS:

• B.Eng (EE/EEE) or similar field and 8+ years’ experience in flip-chip-BGA package design, including high-speed SerDes preferred.
• M.Eng (EE/EEE) or similar field and 6+ years’ experience in flip-chip-BGA package design, including high-speed SerDes preferred.
• Experience with 2.5D and 3DIC packages is highly advantageous.