Principal Package Architect & Tech Leader

1100 Micron SemiAsiaOP Pte Ltd

Singapore

On-site

SGD 180,000 - 320,000

Full time

10 days ago

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Job summary

Micron Technology, Inc. in Singapore seeks an experienced packaging engineer to own architecture from feasibility through tape-out, qualification, and production readiness. You will act as the technical authority across product, silicon, technology, assembly, quality, supplier, and OSAT teams, balancing performance, manufacturability, cost, and schedule.

A Master’s degree and 10+ years’ experience are required, with Cadence Allegro / SiP tools and AI-enabled workflows.

Qualifications

  • Master’s degree in Electrical Engineering or related field.
  • Deep expertise in package architecture and silicon-package co-design.
  • Hands-on experience with multiple package technologies and manufacturability.
  • Proven ownership from feasibility to NPI tape-out and handoff.
  • Advanced proficiency with Cadence Allegro Package Designer / SiP Layout.

Responsibilities

  • Own package architecture from feasibility through tape-out and production readiness.
  • Serve as technical authority for complex package issues across cross-functional teams.
  • Balance performance, reliability, manufacturability, cost, and schedule.
  • Advance design rules, automation workflows, and technology roadmaps.
  • Represent packaging in silicon-package-board co-design and resolve trade-offs.

Skills

Package architecture
Co-design silicon-package
Design verification
Technical leadership
AI literacy

Education

Master’s degree in Electrical Engineering
PhD candidates welcome

Tools

Cadence Allegro Package Designer / SiP Layout

Job description

Micron Technology, Inc. in Singapore seeks an experienced packaging engineer to own architecture from feasibility through tape-out, qualification, and production readiness. You will act as the technical authority across product, silicon, technology, assembly, quality, supplier, and OSAT teams, balancing performance, manufacturability, cost, and schedule.

A Master’s degree and 10+ years’ experience are required, with Cadence Allegro / SiP tools and AI-enabled workflows.

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