Lead Packaging Architect – SiP & Co-Design Expert

MICRON SEMICONDUCTOR ASIA OPERATIONS PTE LTD; Singapore; On-site; SGD 180,000 - 240,000; Full time

Job summary

Micron Technology, Inc. in Singapore seeks a senior packaging architect to own the entire package architecture from feasibility to tape-out and production readiness.

You will drive cross-functional reviews, mentor engineers, and define roadmaps for future products, balancing performance, reliability, and manufacturability. The role requires a PhD or Master’s in engineering with 10+ years of experience in package architecture and silicon–package co-design, including NPI tape-out and manufacturing

Qualifications

• Master’s degree in a relevant engineering field.
• 10+ years in package architecture and silicon–package co-design.
• Hands-on with package technologies and manufacturability.
• Experience with NPI tape-out and manufacturing handoff.

Responsibilities

• Own package architecture and execution from feasibility through tape-out and production readiness.
• Act as technical authority for complex package issues and mentor engineers.
• Advance design rules, methodologies, automation workflows, and roadmaps.
• Represent packaging in silicon–package–board co-design and resolve trade-offs.
• Apply AI literacy to use AI-enabled tools effectively.
• Contribute to continuous AI-enabled improvements within scope.

Skills

Package architecture

Silicon–package design

Feasibility studies

Design verification

Power delivery

Interconnect routing

Mentoring

Stakeholder influence

Education

Master’s degree in Electrical/Mechanical/Materials Eng

Tools

Cadence Allegro Package Designer

Job description

Micron Technology, Inc. in Singapore seeks a senior packaging architect to own the entire package architecture from feasibility to tape-out and production readiness.

You will drive cross-functional reviews, mentor engineers, and define roadmaps for future products, balancing performance, reliability, and manufacturability. The role requires a PhD or Master’s in engineering with 10+ years of experience in package architecture and silicon–package co-design, including NPI tape-out and manufacturing