Principal Engineer - Wafer Bumping R&D

United Test And Assembly Center Limited (UTAC); Singapore; On-site; SGD 180,000 - 240,000; Full time

Job summary

UTAC is seeking a Principal Engineer to lead development, qualification and introduction of advanced wafer bumping technologies. You will drive NPI, process development and technology transfer with customers, suppliers and cross-functional teams to deliver high-yield manufacturing solutions and next-generation packaging.

You will coordinate with internal teams to evaluate materials, processes and equipment, perform DOE and data analysis to ensure robust manufacturing processes, and report

Qualifications

• Bachelor’s degree in Electronics, Mechatronics, Engineering, Materials science or related field.
• 10+ years’ experience in Wafer Bumping Process Development.
• Strong technical expertise in wafer bumping processes and backend packaging technologies.
• Proven track record in developing, qualifying and transferring bumping technologies from R&D to manufacturing.
• Experience with DOE, statistical analysis, process characterization and yield improvement.

Responsibilities

• Lead NPI, package and process development in line with UTAC’s roadmap and schedules.
• Evaluate and qualify new materials, processes, equipment for bumping development.
• Perform DOE, process characterization and data analysis to establish robust processes.
• Coordinate technology transfer and process release to manufacturing.
• Conduct failure analysis and root cause investigation for development issues.
• Track milestones, risks and deliverables with stakeholders and management.
• Collaborate with Manufacturing, Quality, Reliability and Equipment teams to improve capabilities.
• Prepare technical reports and present qualification results to customers and management.
• Provide technical support for customer meetings and qualification activities.
• Drive continuous improvement to bumping process capability and efficiency.

Skills

NPI leadership

Cross-functional collaboration

DOE

Data analysis

Project management

Troubleshooting

Customer/supplier interaction

Education

Bachelor’s degree in Electronics/Mechatronics/Engineering/Materials science

Tools

PVD

Photolithography

Electroplating

Ball Drop

Reflow

UBM formation

WLCSP

Fan-Out packaging

Panel Level Packaging (PLP)

2.5D/3D packaging

Cu Pillar bumping

JMP/Minitab/Python

Job description

Job Summary

As a Principal Engineer, you will lead the development, qualification and introduction of advanced wafer bumping technologies to support UTAC’s technology roadmap and customer requirements. You will drive NPI, process development and technology transfer activities, working closely with customers, suppliers and cross‑functional teams to deliver robust, high‑yield manufacturing solutions and next‑generation packaging technologies.

Responsibilities

• Lead assigned New Product Introduction (NPI), package development and process development activities in accordance with UTAC's technology roadmap, project schedule and business requirements.
• Work closely with internal teams, customers and suppliers to evaluate and qualify new materials, processes, equipment and technologies related to bumping development.
• Execute engineering builds, qualification activities, Design of Experiments (DOE), process characterization and data analysis to establish robust manufacturing processes.
• Coordinate technology transfer and process release to manufacturing, ensuring compliance with UTAC systems, APQP requirements and customer expectations.
• Conduct failure analysis, root cause investigation and corrective/preventive actions for development and qualification issues.
• Monitor and track project milestones, deliverables and technical risks, providing regular progress updates to stakeholders and management.
• Collaborate with Manufacturing, Quality, Reliability and Equipment teams to address technical challenges and improve process capability, yield and productivity.
• Prepare and present technical reports, qualification results, engineering assessments and project updates to customers and management.
• Provide technical support for customer meetings, engineering reviews and qualification activities.
• Drive continuous improvement initiatives and identify opportunities to enhance bumping process capability, reliability and operational efficiency.
• Perform any other duties assigned by the Senior Manager, Bumping R&D or Management from time to time.

Requirements

• Minimum a Bachelor’s degree in Electronics, Mechatronics, Engineering, Material science or any related semiconductor manufacturing discipline.
• At least 10 years’ experience in Wafer Bumping Process Development.
• Strong technical expertise in wafer bumping processes, including PVD, Photolithography, Electroplating, Ball Drop, Reflow, UBM formation, WLCSP and related backend wafer‑level packaging technologies.
• Proven track record in developing, qualifying and transferring new wafer bumping technologies, products and processes from R&D through manufacturing ramp‑up.
• Hands‑on experience in Design of Experiments (DOE), statistical analysis, process characterisation, yield improvement and process optimisation.
• Strong analytical and troubleshooting capabilities with extensive experience in failure analysis, root cause investigation and corrective/ preventive actions (CAPA).
• Experience working with customers, suppliers and equipment vendors on technology evaluation, new process introduction and technical problem resolution.
• Strong project management skills with the ability to manage multiple development programs, priorities and timelines effectively.
• Experience with advanced packaging technologies such as Fan‑Out, Panel Level Packaging (PLP), 2.5D/3D packaging, Cu Pillar bumping or Hybrid Bonding will be an added advantage.
• Familiarity with statistical and data analysis tools such as JMP, Minitab, Python or equivalent engineering analysis software is preferred.