Senior Research Engineer I, Adv Pkg, IME

A*STAR RESEARCH ENTITIES; Singapore; On-site; SGD 65,000 - 90,000; Full time

Job summary

A*STAR RESEARCH ENTITIES in Singapore seeks a talented engineer to drive process integration for high-density multi-chip FOWLP. You will lead development of capable packaging workflows and collaborate with OEMs and internal teams.

The role requires hands-on semiconductor fabrication experience, strong analytical skills, and a passion for mentoring less experienced colleagues. You will publish findings and contribute to workforce development in the field.

Qualifications

• Bachelors/Masters in Materials Science & Engineering, Mechanical or Chemical Engineering, Electronics, or Electrical & Computer Engineering.
• Diploma holder in engineering or science with related experience acceptable.
• 5–10 years in semiconductor device fabrication process integration; wafer-level bumping, RDL, FOWLP experience advantageous.
• Hands-on lithography, plating, etching, and RDL/bumping integration experience.
• Knowledge of wafer-level fabrication and advanced packaging technologies; reliability characterization preferred.
• Strong analytical and problem-solving, with data analysis and DOE design experience.
• Excellent written and verbal communication; able to work in a research-oriented environment and mentor.

Responsibilities

• Process integration development for high density multi-chip FOWLP.
• Develop capabilities such as fine pitch RDL, micro bumping, multi-layer RDL, polymer damascene.
• Establish novel RDL-first and mold-first fan-out integration flows for partners.
• Plan loops and collaborate with process module team for materials evaluation.
• Work with industry partners and multidisciplinary teams to resolve issues.
• Conduct experiments for process characterization to improve quality and yield.
• Coordinate and support engineering builds using developed packaging processes.
• Lead capability development projects and mentor less experienced colleagues.
• Inspire young talent and contribute to workforce development; publish findings.

Skills

Analytical skills

Problem solving

Communication skills

Team collaboration

Heterogeneous integration

FOWLP technologies

Advanced packaging

Education

Bachelor's/Master's in Materials Science & Engineering

Mechanical Engineering

Chemical Engineering

Electronics

Electrical & Computer Engineering

Diploma in engineering/science

Job description

• Process integration development for high density multi-chip fan-out wafer level packaging for various applications such as AI/ HPC, Co-package Optics, Power devices etc.
• Drive the development of new capabilities such as fine pitch RDL, micro bumping, multi-layer RDL, polymer damascene etc required for future FOWLP integration.
• Establish novel RDL-first and mold-first fan-out packaging integration flows to meet industry partners requirements for various applications.
• Plan short loops and work with process module team to develop various processes and materials evaluation for FOWLP.
• Work with industry partners and multidisciplinary team members to execute the projects/assigned tasks by resolving issues.
• Conduct engineering experiments for process characterization to drive quality and yield improvements.
• Coordinate and support engineering build using developed packaging processes and integration.
• Lead industry and internal capability development projects with manageable risks and mentor less experienced colleagues.
• Inspire and mentor young talent in semiconductor technology, contributing to workforce development in the field.
• Publish new findings and technological advancement in prestigious journals and overseas/local conferences.

Job Requirements:

• Bachelors/Masters in Materials Science and Engineering, Mechanical or Chemical Engineering, Electronics, Electrical and Computer Engineering, or Diploma holder with any engineering or science related field.
• 5 to 10 years of experience in any semiconductor devices fabrication process integration, and experience in wafer level bumping, RDL and fan-out wafer level package integration will be added advantage.
• Hands-on experience in semiconductor manufacturing processes such as lithography, plating, etching as well as RDL and bumping process integration.
• Knowledge of wafer level fabrication processes and advanced packaging technologies, methodologies, and reliability characterization is preferable, but not mandatory.
• Strong analytical and problem-solving skills. Proficiency in data analysis and interpretation and design of experiments.
• Excellent written and verbal communication abilities.
• Ability to work collaboratively in a research-oriented environment (OEMs, customers, and Internal stakeholders). Demonstrated ability to manage multiple tasks and projects simultaneously.
• Demonstrated expertise in heterogeneous integration, FOWLP technologies, and advanced packaging processes.