Senior/ Staff NPI Wafer Bumping/Fan-Out Process Engineer

Lumilens; Singapore; Sur place; SGD 90 000 - 135 000; Plein temps

Résumé du poste

Lumilens seeks an experienced engineer to lead wafer bumping and fan-out process development for silicon photonic wafers. You will design and optimize early-stage flows, run DOEs to map process windows, and drive material evaluations including dielectrics and solder alloys.

You will apply reliability plans (TCT, HAST, HTS), perform root-cause analyses, and develop SOPs and WIs for NPI. Strong background in photolithography and PVD/CVD is required.

Qualifications

• Education: Bachelor or Master degree in Materials Science, Chemical Engineering, Mechanical Engineering, Microelectronics, or equivalent.
• Experience: 5+ years hands-on wafer bumping or Fan-out process integration/development, at OSAT or IDM line.
• Deep understanding of photolithography, wet etching, CVD, and PVD.
• Strong knowledge of FPVA/WLCSP techno-mechanisms and process validation methodologies (FMEA, SPC).
• Proficient in statistical tools: JMP, Minitab, Python.

Responsabilités

• Lead process development and technical support for wafer bumping and Fan-Out for silicon photonic chip wafers.
• Design and optimize early-stage process flows; DOE to characterize process window and margin.
• Evaluate and qualify new materials including dielectric photoresists and solder alloys.
• Design DOE plans for reliability: TCT, HAST, HTS; perform root-cause analyses.
• Compile SOPs, work instructions, and change documents; support NPI validation.

Connaissances

Wafer bumping

Fan-out integration

DOE

Process optimization

SPC

FMEA

8D problem solving

Photolithography

CVD

PVD

Warpage analysis

Finite element

Python

JMP

Minitab

Formation

Materials Science

Chemical Engineering

Mechanical Engineering

Microelectronics

Outils

SEM

CSAM

Python

JMP

Minitab

Description du poste

Core Responsibilities

• Lead the process development and technical support of the wafer bumping, and/or Fan-Out process for silicon photonic chip wafers

• Process Pathfinding & Integration: Design and optimize early-stage process flows for wafer bumping, thin-film sputtering, lithography, electroplating, and ball drop execution. DOE to characterize process window and margin.

• Material Characterization & Selection: Evaluate and qualify new manufacturing raw materials, including dielectric photoresists, plating chemistries, underfills, and solder alloys.

• Reliability & Stress Engineering: Design and execute DOE plans to characterize thermal and mechanical stress. Lead reliability validations including Temperature Cycling Test (TCT), Unbiased Highly Accelerated Stress Test (HAST) and High-Temperature Storage (HTS).

• Failure Analysis & Debug: Own the root-cause diagnostics of structural failure modes unique to WLCSP (e.g., RDL cracking, bridging ball bridging, bump missing, delamination, or wafer warpage). Utilize specialized analytics instrumentation including SEM, CSAM, and physical cross-sectioning. Conduct root cause analysis and formulate improvement solutions.

• Optimize key bumping process parameters including wafer cleaning, UBM sputtering, solder ball plating, reflow and bump inspection to improve bump uniformity and yield.

• Manage incoming wafer quality control, establish SPC control plans and monitor process variation to ensure long-term process stability

• Compile process SOP, WI, process failure reports and engineering change documents; support NPI new product introduction and process verification.

Required Qualifications

• Education: Bachelor or Master degree in Materials Science, Chemical Engineering, Mechanical Engineering, Microelectronics, or an equivalent technical discipline.

• Experience: 5+years of hands-on wafer bumping or Fan-out process integration or development experience, at OSAT or IDM internal advanced packaging line. Process exposure/experience on interposer, 2.5D/3D, chip on wafers on substrate, will be an added advantage.

• Technical Knowledge:

  • Deep practical understanding of photolithography, wet etching, chemical vapor deposition (CVD), and physical vapor deposition (PVD), moulding process adapted for backend bump fabrication.

  • Comprehensive command of finite element simulation principles regarding warpage, thermal dissipation, and structural mechanical integrity.

  • Solid working expertise with industry validation methodologies including FMEA, SPC controls, and structured 8D problem-solving tools.

  • Software Tools: High proficiency with robust analytical platforms like JMP, Minitab, or Python.