Senior/ Staff NPI Wafer Bumping/Fan-Out Process Engineer

Lumilens; Singapore; Presencial; SGD 90 000 - 150 000; Tempo integral

Resumo da oferta

Lumilens Inc. in Singapore is seeking an experienced Process Engineer to lead wafer bumping and Fan-Out process development for silicon photonic chip wafers. You will design and optimize early-stage flows, perform DOE, and drive process reliability and yield improvements.

The role requires a strong background in materials science or microelectronics, 5+ years in advanced packaging, and hands-on experience with interposers and 2.5D/3D integration, with a focus on quality and process control.

Qualificações

• Bachelor or Master in Materials Science, Chemical Engineering, Mechanical Engineering or Microelectronics.
• 5+ years hands-on wafer bumping or Fan-Out process integration experience.
• Experience with interposer, 2.5D/3D packaging and related wafer-on-substrate concepts.

Responsabilidades

• Lead process development and technical support for wafer bumping and Fan-Out for silicon photonic wafers.
• Design and optimize early-stage process flows including lithography, sputtering, electroplating, and ball drop.
• DOE to characterize process window and margin; drive yield improvements.
• Evaluate materials such as dielectric photoresists, plating chemistries, underfills, and solder alloys.
• Plan and execute reliability tests (TCT, HAST, HTS) and conduct stress analyses.
• Own root-cause analysis for failures (RDL cracking, bump issues) using SEM and CSAM.
• Optimize bumping parameters and monitor process variation with SPC control plans.
• Document SOPs, WIs, failure reports, and support NPI/process verification.

Conhecimentos

Wafer bumping

Fan-out packaging

DOE

Process optimization

Statistical analysis

Interposer & 2.5D/3D exposure

Reliability testing

SEM & CSAM instrumentation

Formação académica

Bachelor or Master in Materials Science

Chemical Engineering

Mechanical Engineering

Microelectronics

Ferramentas

SEM

CSAM

Cross-sectioning

Descrição da oferta de emprego

Core Responsibilities

• Lead the process development and technical support of the wafer bumping, and/or Fan-Out process for silicon photonic chip wafers

• Process Pathfinding & Integration: Design and optimize early-stage process flows for wafer bumping, thin-film sputtering, lithography, electroplating, and ball drop execution. DOE to characterize process window and margin.

• Material Characterization & Selection: Evaluate and qualify new manufacturing raw materials, including dielectric photoresists, plating chemistries, underfills, and solder alloys.

• Reliability & Stress Engineering: Design and execute DOE plans to characterize thermal and mechanical stress. Lead reliability validations including Temperature Cycling Test (TCT), Unbiased Highly Accelerated Stress Test (HAST) and High-Temperature Storage (HTS).

• Failure Analysis & Debug: Own the root-cause diagnostics of structural failure modes unique to WLCSP (e.g., RDL cracking, bridging ball bridging, bump missing, delamination, or wafer warpage). Utilize specialized analytics instrumentation including SEM, CSAM, and physical cross-sectioning. Conduct root cause analysis and formulate improvement solutions.

• Optimize key bumping process parameters including wafer cleaning, UBM sputtering, solder ball plating, reflow and bump inspection to improve bump uniformity and yield.

• Manage incoming wafer quality control, establish SPC control plans and monitor process variation to ensure long-term process stability

• Compile process SOP, WI, process failure reports and engineering change documents; support NPI new product introduction and process verification.

Required Qualifications

• Education: Bachelor or Master degree in Materials Science, Chemical Engineering, Mechanical Engineering, Microelectronics, or an equivalent technical discipline.

• Experience: 5+years of hands-on wafer bumping or Fan-out process integration or development experience, at OSAT or IDM internal advanced packaging line. Process exposure/experience on interposer, 2.5D/3D, chip on wafers on substrate, will be an added advantage.

• Technical Knowledge: