Associate Staff Digital Engineer

SILICON LABORATORIES INTERNATIONAL PTE. LTD.; Serangoon Garden Circus; On-site; SGD 80,000 - 100,000; Full time

Job summary

A leading technology firm in Singapore is looking for an experienced Design Engineer to join the Silicon Engineering team. The role involves driving the design and optimization of advanced SoCs using physical design methodologies. The ideal candidate will possess a strong background in ASIC physical design with hands-on experience in EDA tools, and will collaborate with cross-functional teams. The position offers competitive benefits including medical insurance and stock purchase programs.

Benefits

Employee Stock Purchase Program (ESPP)

Medical and dental insurance

Bi-yearly health screening

Flu vaccination

Office located above Tai Seng MRT station

Qualifications

• Bachelors or Masters in Electrical Engineering, VLSI, or related.
• Over 4 years of ASIC physical design experience required.
• Hands-on experience with Synopsys and Cadence EDA tools.

Responsibilities

• Drive design and optimization of SoCs using physical design methodologies.
• Execute physical design flow from RTL to GDSII.
• Collaborate with teams for design integration.

Skills

End-to-end physical design flow execution

Floorplanning

Timing closure strategies

Power performance area optimization

Collaboration with RTL and verification teams

EDA tool automation

Mentoring junior engineers

Process technology collaboration

Education

Bachelor's or Master's degree in Electrical Engineering, VLSI, or related field

4+ years of experience in ASIC physical design

Tools

Synopsys (ICC2, Fusion Compiler, PrimeTime)

Cadence (Innovus, Tempus)

Job description

What we’re looking for:

We are seeking a highly skilled Design Engineer to join our Silicon Engineering team. This role involves driving the design, implementation, and optimization of cutting‑edge SoCs through advanced physical design methodologies. The ideal candidate will have deep expertise in synthesis, floorplanning, place‑and‑route, timing closure, power/performance optimization, and sign‑off flows.

Skills you’ll need:

• Execute the end‑to‑end physical design flow for complex SoCs and IP blocks (from RTL handoff to GDSII).

• Define and drive floorplanning, clock‑tree synthesis (CTS), placement, routing, and timing closure strategies.

• Own and optimize power, performance, and area (PPA) metrics for assigned designs.

• Manage design constraints, synthesis strategies, and sign‑off criteria (timing, IR drop, EM, DRC/LVS).

• Collaborate with front‑end RTL, DFT, verification, and packaging teams to ensure seamless integration.

• Drive EDA tool flow automation and methodology enhancements for improved efficiency and scalability.

• Mentor and guide junior engineers, fostering technical growth and design excellence.

• Work closely with foundries and vendors on process technology bring‑up, PDK updates, and tape‑out readiness.

Education and/or Experience:

• Bachelor’s or Master’s degree in Electrical Engineering, VLSI, or related field.

• 4+ years of experience in ASIC physical design

• Hands‑on expertise in EDA tools: Synopsys (ICC2, Fusion Compiler, PrimeTime)

• Cadence (Innovus, Tempus), or equivalent.

• Strong background in timing analysis, low‑power methodologies, and ECO flows.

• Solid understanding of architecture‑to‑GDSII flows and sign‑off requirements.

• Experience with chip‑level integration and hierarchical design methodologies.

• Knowledge of low‑power design techniques (UPF/CPF, power gating, DVFS).

• Familiarity with DFT, STA, and physical verification methodologies.

• Exposure to multi‑clock, multi‑voltage, and multi‑domain designs.

• Excellent problem‑solving and communication skills.

Benefits & Perks:

Not only will you be joining a highly skilled and tight‑knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.

• Employee Stock Purchase Program (ESPP)
• Medical and dental insurance coverage including spouse and child(ren)
• Bi‑yearly health screening and flu vaccination
• Office location is above Tai Seng MRT station