ASIC/SoC Design Verification Engineer SG

Tetramem; Singapore; On-site; SGD 80,000 - 180,000; Full time

Job summary

A leading AI technology firm in Singapore is seeking an experienced Verification Engineer to work on SoC design verification. The ideal candidate will have a Master's or Ph.D. in Electrical Engineering or related fields, along with extensive experience in UVM/OVM and verification methodologies. You will collaborate closely with design engineers, develop infrastructure for automated verification, and mentor junior team members. This role offers a competitive salary range and the chance to work at the forefront of AI innovations.

Qualifications

• MS with 8+ years of relevant experience or PhD with 3+ years.
• Knowledge of UVM/OVM and verification methodologies.
• Extensive experience in test planning and coverage closure.

Responsibilities

• Collaborate with design engineers on test plans.
• Build infrastructure for automation verification.
• Mentor team members while driving verification efficiency.

Skills

UVM/OVM

Test planning

Verilog

System Verilog

Python

C/C++

Scripting

Education

MS in Electrical Engineering or related

PhD in Electrical Engineering or related

Tools

Semiformal Verification tools

Testbench development tools

Job description

At TetraMem, we are redefining the future of AI with our groundbreaking innovations in In-Memory Computing. Leveraging world-record multi-level RRAM technology, we deliver highly efficient solutions for AI computations, enabling superior performance and energy efficiency across applications ranging from edge devices to data centers.

Our talented team of engineers and industry-leading executives drives this progress, making TetraMem a leader in advanced memory technologies.

If you are passionate about cutting‑edge technology and thrive in a fast‑paced, collaborative environment, TetraMem is the place for you. Join our global team to shape the future of AI computations and sustainable technology solutions while working at the forefront of innovation. Together, we can make a lasting impact.

Are you ready for new challenges and new opportunities?

Join our team!

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Responsibilities

• Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification
• Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance
• Develop reusable testbench, constrained-random/directed testcases, and verification associated behavioral module for both of block levels and system levels
• Develop regression strategy, methodology and tools(scripts). Define and measure the function coverage. Close verification holes for design releases and tape‑out
• Work with design engineers to debug and identify root causes of simulation failure
• Support test engineers for post‑silicon validation
• Mentor and coach team members and junior engineers. Drive verification efficiency

Requirements

• MS with 8+ years of relevant experience or PhD (with 3+ years of experience) in Electrical Engineering, Computer Engineering, Computer Science or related degree
• In depth knowledge of UVM/OVM, Semiformal Verification, assertion-based verification as well as hardware and software co-verification methodology
• Extensive experience of building verification infrastructure, test planning, coverage closure, testbench and testcases development for function/performance verification
• Proficient experience with Verilog, System Verilog, Python/Perl/TCL/Shell scripting, C/C++, System C and industry mainstream ISAs assembly coding
• Familiarity with MIPI, AMBA (APB/AHB/AXI) bus protocol, RISC‑V/ARM or DSP core
• Experience in verifying designs at both of RTL level and post‑P&R gate level
• Ability to work in a startup environment, and to work both independently and as a team player with the ability to provide technical leadership to other members of the engineering team

Experience in one or more of the following areas considered a strong plus

• Working knowledge of AI/ML Computing, GPU, ISP architectures and accelerators
• Experience in verifying mix-signal design and interface of digital and analog
• Experience of design verification for highspeed IO such as PCIE and DDR

Salary Range: S$80,000 - S$180,000 / year