Senior Physical Design Engineer - Hybrid, Growth & Impact

Capgemini Engineering; Vila Nova de Gaia; Ibrido; EUR 70.000 - 95.000; Tempo pieno

Vantaggi offerti da questo lavoro

Health and life insurance

Hybrid work

Referral program with bonuses for tal­

Descrizione del lavoro

Capgemini Engineering in Porto, Portugal, is seeking a Senior Physical Design Engineer to drive physical design across the implementation flow from floorplanning to tape-out. You will work on complex 10nm+ ASIC designs, leading floorplanning, CTS, routing and timing closure while ensuring power integrity and ECOs.

The ideal candidate has 6+ years in physical design, strong scripting skills (Perl, TCL, Python, Makefile), and experience with Synopsys/Cadence tools.

Competenze

• Bachelor’s or Master’s degree in Electrical or Computer Engineering or related field.
• 6+ years of experience in Physical Design or ASIC implementation.

Mansioni

• Drive physical design activities from floorplanning through sign-off and tape-out.
• Perform block and full-chip Physical Design using advanced technology nodes (10nm and below).
• Lead floorplanning, partitioning, power planning, placement, CTS, routing and optimization.
• Drive timing analysis and timing closure including signal integrity and noise analysis.
• Generate and implement functional and timing ECOs and perform physical verification (DRC/LVS/EM/IR).
• Work on low power design implementation and related methodologies.
• Develop scripts for clock skew analysis, critical path analysis, I/O interfaces and budgeting.”
• Support sign-off and tape-out activities and collaborate with multidisciplinary teams.

Conoscenze

Synopsys tools

Cadence tools

Scripting (Perl, TCL, Python, Makefile

Formazione

Bachelor’s or Master’s in Electrical or Computer Engineering

Strumenti

Physical Design tools

Descrizione del lavoro

Capgemini Engineering in Porto, Portugal, is seeking a Senior Physical Design Engineer to drive physical design across the implementation flow from floorplanning to tape-out. You will work on complex 10nm+ ASIC designs, leading floorplanning, CTS, routing and timing closure while ensuring power integrity and ECOs.

The ideal candidate has 6+ years in physical design, strong scripting skills (Perl, TCL, Python, Makefile), and experience with Synopsys/Cadence tools.