Analog Ic Layout Engineer (Mid/Senior-Level)

Caravel Semiconductor; Porto; Hybrid; EUR 40,000 - 70,000; Full time

Benefits offered by this job

Hybrid work schedule

Job summary

Caravel Semiconductor in Porto, Portugal, is seeking an analog layout engineer to turn designs into silicon-ready layouts—from floorplan to tape-out-clean GDS. You will own layout of LDOs, references, amplifiers, PLLs and RF blocks, collaborating closely with circuit designers.

We offer hybrid work (two days a week in Porto, remaining remote) and a path to impact across regulators, references, PLLs, RF and data converters.

Qualifications

• BSc or MSc in Electrical Engineering, Microelectronics or related field.
• 1–5 years hands-on analog layout experience.
• Solid grasp of analog layout fundamentals: matching, parasitics, latch-up, ESD, electromigration and IR drop, DFM.
• Experience with full-custom layout flow and verification tools (Calibre, PVS).
• Good written and spoken English.
• Based in, or willing to relocate to, the Porto area.

Responsibilities

• Layout analog and mixed-signal blocks from floorplan to final GDS: matching, symmetry, common-centroid and interdigitated structures, guard rings, shielding.
• Plan floorplans with the designer: pin placement, current paths, IR drop and electromigration.
• Run and close physical verification: DRC, LVS, antenna, density and extract parasitics to iterate on post-layout results with the designer.
• Build top-level integration: block abutment, power and ground routing, pad ring and ESD, chip finishing (seal ring, fill, metal density).
• Help set up PDKs and layout tools for new projects together with the design team.

Skills

Analog layout

Full-custom flow

English

Education

BSc/MSc in Electrical Engineering

Tools

Cadence Virtuoso Layout

Synopsys Custom Compiler

Calibre

PVS

Job description

Caravel Semiconductor is a Portuguese analog and mixed-signal IC design house. We design analog IP like PLLs and oscillators, regulators and references, RF front-ends, data converters and ESD for clients in the semiconductor space.

The role

We're looking for an analog layout engineer to turn our designers' schematics into silicon-ready layout: LDOs, references, comparators, amplifiers, PLLs, and RF blocks. You'll own layout from floorplan to tape-out-clean GDS, working side by side with the circuit designers.

What you'll do

• Layout analog and mixed-signal blocks from floorplan to final GDS: matching, symmetry, common-centroid and interdigitated structures, guard rings, shielding
• Plan floorplans with the designer: pin placement, current paths, IR drop and electromigration
• Run and close physical verification: DRC, LVS, antenna, density and extract parasitics to iterate on post-layout results with the designer
• Build top-level integration: block abutment, power and ground routing, pad ring and ESD, chip finishing (seal ring, fill, metal density)
• Help set up PDKs and layout tools for new projects together with the design team

What we’re looking for

• BSc or MSc in Electrical Engineering, Microelectronics or a related field, or equivalent hands-on experience
• 1-5 years of hands-on analog layout experience (thesis work and internships count for junior candidates)
• Solid grasp of analog layout fundamentals: matching, parasitics, latch-up, ESD, electromigration and IR drop, DFM
• Working knowledge of a full-custom layout flow: Cadence Virtuoso Layout, Synopsys Custom Compiler or an equivalent environment and a physical verification tool (Calibre, PVS or similar)
• Good written and spoken English
• Based in, or willing to relocate to, the Porto area

Nice to have

• RF or high-speed layout: inductors and transformers, matched differential routing, shielding
• Top-level chip assembly and tape-out experience
• Familiarity with the Synopsys custom design flow alongside the Cadence one
• Comfortable working in a Linux environment (shell, remote compute)
• Scripting for layout automation (SKILL, Python, TCL)

What we offer

• Hybrid work: 2 days a week at the Porto office, the rest remote
• Layout responsibility from day one, with senior engineers alongside you
• A broad portfolio: regulators, references, PLLs, RF, data converters, ESD - so no two blocks look the same
• A small team where your work goes to silicon, with no layers between you and the tape-out