Senior FPGA Architect: PCIe Prototyping & Verification

Synopsys, Inc.; Moreira; Vor Ort; EUR 70.000 - 100.000; Vollzeit

Zusammenfassung

Synopsys Porto is seeking an experienced FPGA engineer to design high-performance PCIe solutions. You will contribute across the full RTL lifecycle from architecture through timing closure and hardware bring-up, delivering reliable prototypes on aggressive schedules.

You will collaborate with hardware, software, and verification teams, apply structured debugging, and participate in industry compliance activities.

Qualifikationen

• Bachelor's or Master's in Electrical/Computer Engineering or equivalent hands-on experience.
• 8+ years FPGA design and development experience with shipping designs.
• Strong Verilog RTL design skills and timing closure know-how.

Aufgaben

• Prototype and optimize PCIe-based designs on FPGA platforms using Vivado.
• Simulate and verify designs using UVM and related methodologies.
• Perform timing analysis across clock domains to meet targets.
• Collaborate with hardware, software and verification teams to define requirements.
• Develop test plans to validate functionality and reliability of FPGA prototypes.
• Participate in PCI-SIG compliance testing and resolve issues.

Kenntnisse

Verilog

RTL design

PCIe

Multi-clock domain design

Debugging hardware

Ausbildung

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Vivado

Python

Tcl

Jobbeschreibung

Synopsys Porto is seeking an experienced FPGA engineer to design high-performance PCIe solutions. You will contribute across the full RTL lifecycle from architecture through timing closure and hardware bring-up, delivering reliable prototypes on aggressive schedules.

You will collaborate with hardware, software, and verification teams, apply structured debugging, and participate in industry compliance activities.