ASIC Digital Design, Sr Staff Engineer

Synopsys, Inc.; Porto; Híbrido; EUR 55 000 - 85 000; Tempo integral

Resumo da oferta

Synopsys, Inc. in Porto, Portugal seeks a highly skilled Verification Engineer to lead ASIC digital verification with HBM protocol expertise. You will design verification plans, build testbenches with SystemVerilog and UVM, and collaborate with design teams to meet specifications.

You will debug complex ASIC issues, optimize verification environments, and mentor junior engineers, contributing to high-performance silicon chip validation and overall product quality.

Qualificações

• Extensive ASIC digital verification experience with HBM protocols.
• Proficiency in SystemVerilog, UVM and verification methodologies.
• Strong understanding of digital design and verification processes.
• Experience with simulation and debugging techniques.

Responsabilidades

• Develop and execute verification plans for ASIC designs.
• Create and maintain testbenches using SystemVerilog and UVM.
• Collaborate with design and architecture teams to interpret specs.
• Identify, isolate, and debug issues in complex ASICs.
• Enhance verification environments and test suites.
• Review design and verification documentation.
• Mentor and guide junior verification engineers.

Conhecimentos

SystemVerilog

UVM

ASIC verification

HBM protocols

Testbenches

Debugging

Simulation tools

Mentoring

Collaboration

Descrição da oferta de emprego

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a highly skilled Verification Engineer with significant experience in ASIC digital verification and a deep understanding of HBM protocols. You thrive in complex problem-solving environments and are adept at working with sophisticated verification methodologies. You have a knack for identifying and addressing verification challenges, ensuring the delivery of high-quality, reliable products. Your collaborative spirit and excellent communication skills enable you to work effectively with cross-functional teams, driving project success through innovation and technical excellence.

You possess a strong foundation in digital design and verification, along with substantial experience in creating and executing verification plans. Your expertise in SystemVerilog, UVM, and other verification tools is complemented by your ability to mentor and guide junior engineers. You are proactive, detail-oriented, and committed to continuous learning and improvement, always staying abreast of the latest industry trends and technologies.

What You’ll Be Doing:

• Developing and executing comprehensive verification plans for ASIC designs.
• Creating and maintaining testbenches using SystemVerilog and UVM methodologies.
• Collaborating with design and architecture teams to understand design specifications and requirements.
• Identifying, isolating, and debugging issues in complex ASIC designs.
• Implementing and optimizing verification environments and test suites.
• Reviewing and providing feedback on design and verification documentation.
• Mentoring and guiding junior verification engineers.

The Impact You Will Have:

• Ensuring the reliability and performance of Synopsys' high-performance silicon chips.
• Contributing to the successful delivery of cutting-edge technology solutions.
• Enhancing the efficiency and effectiveness of the verification process.
• Driving innovation and excellence within the verification team.
• Improving overall product quality and customer satisfaction.
• Fostering a culture of continuous improvement and technical growth.

What You’ll Need:

• Extensive experience in ASIC digital verification, particularly with HBM protocols.
• Proficiency in SystemVerilog, UVM, and other verification tools and methodologies.
• Strong understanding of digital design principles and verification processes.
• Experience with simulation tools and debugging techniques.