Staff Verification Architect — FPGA/SoC IPs

Lattice Semiconductor; George Town; On-site; MYR 180,000 - 300,000; Full time

Job summary

Lattice Semiconductor in Malaysia is seeking an experienced verification engineer to lead the verification of FPGA/ASIC IPs, subsystems, and SoCs. You will define strategies, supervise sign-off, and mentor junior engineers.

The role requires deep SystemVerilog/UVM expertise, strong debugging skills, and the ability to collaborate across RTL, firmware, and program management to ensure on-time, high-quality silicon delivery.

Qualifications

• Bachelor's or Master's degree in Electrical/Electronic Engineering, Computer Engineering, or related field.
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Responsibilities

• Lead verification planning, execution, and sign-off for complex FPGA/ASIC IPs, subsystems, and SoC-level designs.
• Define verification methodologies, test strategies, coverage goals, and closure criteria for project deliverables.
• Architect and develop SystemVerilog/UVM verification environments, reusable verification components, scoreboards, assertions, and coverage models.
• Drive verification closure through functional coverage, code coverage, regression analysis, and risk assessments.
• Lead debug of complex RTL, integration, low-power, timing, and gate-level simulation issues.
• Collaborate with architects, RTL designers, validation engineers, firmware teams, and program managers to ensure successful product execution.
• Provide technical leadership for verification methodologies, automation, infrastructure, and best practices across projects.
• Mentor and guide verification engineers, perform design and verification reviews, and drive team technical excellence.
• Support silicon bring-up, failure analysis, and root-cause investigations as required.
• Drive continuous improvements in verification productivity, quality, and reusability.

Skills

SystemVerilog

UVM

Assertion-based verification

Constrained-random verification

Coverage-driven verification

Python

Perl

Shell

Strong debugging

Cross-functional collaboration

Education

Bachelor's or Master's in Electrical/Electronic Engineering or Computer Engineering

Job description

Lattice Semiconductor in Malaysia is seeking an experienced verification engineer to lead the verification of FPGA/ASIC IPs, subsystems, and SoCs. You will define strategies, supervise sign-off, and mentor junior engineers.

The role requires deep SystemVerilog/UVM expertise, strong debugging skills, and the ability to collaborate across RTL, firmware, and program management to ensure on-time, high-quality silicon delivery.