FPGA/ASIC Verification Engineer (SystemVerilog/UVM)

Lattice Semiconductor; George Town; On-site; MYR 60,000 - 120,000; Full time

Job summary

Lattice Semiconductor in Penang, Malaysia is seeking a verification engineer to verify IP blocks and full-chip FPGA/ASIC designs. You will define test plans and develop SystemVerilog/UVM testbenches to ensure robust design validation.

Collaborate with architects, RTL designers, and automation engineers to improve coverage and sign off. A Bachelor's degree in Electronic Engineering and at least 2 years in semiconductors are required, with experience in Ethernet, PCIe, DDR, and related FPGA

Qualifications

• Bachelor's degree in Electronic Engineering or related field (required).
• 2+ years of semiconductor or related industry experience.
• Experience with SystemVerilog, UVM, constrained-random verification, and assertion-based methodologies is highly desirable.

Responsibilities

• Verify various IP blocks and full-chip FPGA/ASIC designs.
• Define test plans and develop SystemVerilog/UVM testbenches and test content.
• Debug failures and run regressions to deliver high-quality design validation.
• Work closely with architects, RTL designers, DFX engineers, and automation engineers to ensure robust verification coverage and quality signoff.

Skills

SystemVerilog/UVM

Constrained-random verification

Assertion-based methodologies

Ethernet

PCIe

DDR

Video IP

Education

Bachelor's degree in Electronic Engineering or related field

Job description

Lattice Semiconductor in Penang, Malaysia is seeking a verification engineer to verify IP blocks and full-chip FPGA/ASIC designs. You will define test plans and develop SystemVerilog/UVM testbenches to ensure robust design validation.

Collaborate with architects, RTL designers, and automation engineers to improve coverage and sign off. A Bachelor's degree in Electronic Engineering and at least 2 years in semiconductors are required, with experience in Ethernet, PCIe, DDR, and related FPGA