Lead FPGA/SoC Verification Architect

Lattice Semiconductor; George Town; On-site; MYR 180,000 - 240,000; Full time

Job summary

Lattice Semiconductor is seeking an experienced verification engineer in Malaysia (Penang) to lead verification of complex FPGA/ASIC IPs and SoCs. You will design scalable SystemVerilog/UVM environments, drive coverage, and collaborate with architects and firmware teams to ensure project success.

The role requires strong SystemVerilog/UVM expertise, 5+ years in ASIC/FPGA verification, and experience with industry-standard simulators.

Qualifications

• Bachelor's or Master's degree in Electrical/Electronic Engineering, Computer Engineering, or a related field.
• 5+ years of experience in ASIC/FPGA functional verification.
• Strong expertise in SystemVerilog and UVM.
• Experience developing verification environments including drivers, monitors, scoreboards, assertions, and coverage models.
• Strong debugging skills across RTL, gate-level, and system-level simulations.
• Experience with industry-standard simulators and verification tools.
• Strong scripting skills in Python, Perl, Shell, or equivalent.

Responsibilities

• Lead verification of complex FPGA/ASIC IPs, subsystems, and SoC features from specification through tape-out.
• Develop verification strategies, test plans, and verification closure criteria aligned with product requirements.
• Architect and develop scalable SystemVerilog/UVM-based verification environments, checkers, assertions, scoreboards, and coverage models.
• Drive constrained-random and directed verification to achieve functional and code coverage goals.
• Debug design, testbench, simulation, and integration issues across RTL, GLS, low-power, and system-level verification environments.
• Collaborate closely with architects, design engineers, firmware engineers, and validation teams to ensure successful project execution.
• Drive verification sign-off activities, including coverage closure, regression analysis, and risk assessment.
• Mentor junior verification engineers and contribute to verification methodology improvements and reusable infrastructure.
• Support silicon bring-up and root-cause analysis when required.

Skills

SystemVerilog

UVM

Python scripting

RTL debugging

Verification envs

Education

Bachelor's or Master's degree in Electrical/Electronic Engineering, Computer Engineering, or a related field

Tools

ModelSim

VCS

Xcelium

Job description

Lattice Semiconductor is seeking an experienced verification engineer in Malaysia (Penang) to lead verification of complex FPGA/ASIC IPs and SoCs. You will design scalable SystemVerilog/UVM environments, drive coverage, and collaborate with architects and firmware teams to ensure project success.

The role requires strong SystemVerilog/UVM expertise, 5+ years in ASIC/FPGA verification, and experience with industry-standard simulators.