Senior FPGA/ASIC Verification Lead

Lattice Semiconductor Corp.; George Town; Hybrid; MYR 120,000 - 180,000; Full time

Job summary

Lattice Semiconductor Corp. in Penang, Malaysia, is seeking a Senior Design Verification Engineer to lead verification of complex FPGA/ASIC IPs and subsystems from specification through tape-out.

You will architect scalable SystemVerilog/UVM environments and drive coverage goals with constrained-random and directed approaches. Qualifications include a 5+ year track record in ASIC/FPGA verification, proficiency in SystemVerilog/UVM, and strong scripting skills.

Qualifications

• Bachelor's or master's degree in Electrical/Electronic Engineering or Computer Engineering.
• 5+ years of ASIC/FPGA verification experience.
• Strong SystemVerilog and UVM expertise; experience with simulators and testbench environments.

Responsibilities

• Lead verification of FPGA/ASIC IPs and SoC features from spec to tape-out.
• Develop verification strategies, test plans and closure criteria aligned with product requirements.
• Architect and develop SystemVerilog/UVM-based verification environments, checkers, scoreboards, and coverage models.

Skills

SystemVerilog

UVM

Python

Perl

Shell

Education

BSc/ MSc in EE/ CE

Tools

Testbench

Coverage tools

Job description

Lattice Semiconductor Corp. in Penang, Malaysia, is seeking a Senior Design Verification Engineer to lead verification of complex FPGA/ASIC IPs and subsystems from specification through tape-out.

You will architect scalable SystemVerilog/UVM environments and drive coverage goals with constrained-random and directed approaches. Qualifications include a 5+ year track record in ASIC/FPGA verification, proficiency in SystemVerilog/UVM, and strong scripting skills.