Verification Engineer—SystemVerilog/UVM (FPGA/ASIC)

Lattice Semiconductor Corp.; George Town; Hybrid; MYR 89,000 - 156,000; Full time

Job summary

Lattice Semiconductor Corp. is seeking a Design Verification Engineer in Penang, Malaysia. You will verify IP blocks and full-chip FPGA/ASIC designs, define test plans, and develop SystemVerilog/UVM testbenches, collaborating with architects and DFX to ensure robust coverage and signoff.

The role requires a Bachelor's in Electronic Engineering, with experience in Ethernet, PCIe, JESD, CPRI, DDR, and FPGA technologies. A strong emphasis on test planning and coverage is essential.

Qualifications

• Bachelor's degree in Electronic Engineering or related field.

Responsibilities

• Verify various IP blocks and full-chip FPGA/ASIC designs.
• Define test plans and develop SystemVerilog/UVM testbenches and test content.
• Debug failures and run regressions to deliver high-quality design validation.
• Work closely with architects, RTL designers, DFX engineers, and automation engineers to ensure robust verification coverage and quality signoff.

Skills

Ethernet PCIe JESD CPRI DDR Video IP

SystemVerilog

UVM

Constrained-random verification

Assertion-based verification

Test planning

Testbench development

Functional coverage

Education

Bachelor's degree in Electronic Engineering

Tools

SystemVerilog

UVM

Job description

Lattice Semiconductor Corp. is seeking a Design Verification Engineer in Penang, Malaysia. You will verify IP blocks and full-chip FPGA/ASIC designs, define test plans, and develop SystemVerilog/UVM testbenches, collaborating with architects and DFX to ensure robust coverage and signoff.

The role requires a Bachelor's in Electronic Engineering, with experience in Ethernet, PCIe, JESD, CPRI, DDR, and FPGA technologies. A strong emphasis on test planning and coverage is essential.