Senior FPGA/ASIC Verification Lead (SystemVerilog/UVM)

Lattice Semiconductor Corp.; Malaysia; Hybrid; MYR 120,000 - 180,000; Full time

Job summary

Lattice Semiconductor Corp. in Penang, Malaysia seeks a Senior Design Verification Engineer to lead verification of FPGA/ASIC IPs and subsystems from spec through tape-out.

The role requires building scalable UVM environments, scoreboards, and coverage models, with strong SystemVerilog expertise. You will drive constrained-random verification, collaborate across RTL, GLS, firmware and validation teams, and mentor junior engineers to improve verification methodology.

Qualifications

• 5+ years of ASIC/FPGA functional verification experience.
• Experience with industry-standard simulators and verification tools.
• Strong scripting skills in Python, Perl, Shell, or equivalent.

Responsibilities

• Lead verification of complex FPGA/ASIC IPs, subsystems, and SoC features from specification through tape-out.
• Develop verification strategies, test plans, and verification closure criteria aligned with product requirements.
• Architect and develop scalable SystemVerilog/UVM-based verification environments, checkers, assertions, scoreboards, and coverage models.
• Drive constrained-random and directed verification to achieve functional and code coverage goals.
• Debug design, testbench, simulation, and integration issues across RTL, GLS, low-power, and system-level verification environments.
• Collaborate with architects, design engineers, firmware engineers, and validation teams to ensure project success.
• Drive verification sign-off activities, including coverage closure, regression analysis, and risk assessment.
• Mentor junior verification engineers and contribute to methodology improvements.

Skills

SystemVerilog

UVM

Verification environments

Python scripting

Debugging

RTL/GLS

Education

Bachelor's or Master's in Electrical/Electronic Eng or Computer Eng

Tools

Verilog simulators

VCS/Verilator/ Questa

Job description

Lattice Semiconductor Corp. in Penang, Malaysia seeks a Senior Design Verification Engineer to lead verification of FPGA/ASIC IPs and subsystems from spec through tape-out.

The role requires building scalable UVM environments, scoreboards, and coverage models, with strong SystemVerilog expertise. You will drive constrained-random verification, collaborate across RTL, GLS, firmware and validation teams, and mentor junior engineers to improve verification methodology.