FPGA/ASIC Verification Engineer

Lattice Malaysia; Malaysia; On-site; MYR 60,000 - 100,000; Full time

Job summary

Lattice Malaysia is seeking an experienced verification engineer to validate FPGA/ASIC designs, develop SystemVerilog/UVM testbenches, and run rigorous regressions. You will collaborate with architects, RTL designers, DFX engineers, and automation engineers to ensure high-quality signoff.

The role requires a strong background in SystemVerilog, UVM, and constrained-random verification, with familiarity in Ethernet, PCIe, DDR, and related protocols.

Qualifications

• Bachelor's degree in Electronic Engineering or related field.
• Minimum 2 years of semiconductor or related industry experience.
• Familiarity with Ethernet, PCIe, JESD, CPRI, DDR, Video IP, and FPGA technologies.
• Experience with SystemVerilog, UVM, constrained-random verification, and assertion-based methodologies is highly desirable.

Responsibilities

• Verify various IP blocks and full-chip FPGA/ASIC designs.
• Define test plans and develop SystemVerilog/UVM testbenches and test content.
• Debug failures and run regressions to deliver high-quality design validation.
• Work closely with architects, RTL designers, DFX engineers, and automation engineers to ensure robust verification coverage and quality signoff.

Skills

SystemVerilog

UVM

Testbench development

Debugging

Education

Bachelor's degree in Electronic Engineering or related field

Tools

Verilog/UVM tooling

Job description

Lattice Malaysia is seeking an experienced verification engineer to validate FPGA/ASIC designs, develop SystemVerilog/UVM testbenches, and run rigorous regressions. You will collaborate with architects, RTL designers, DFX engineers, and automation engineers to ensure high-quality signoff.

The role requires a strong background in SystemVerilog, UVM, and constrained-random verification, with familiarity in Ethernet, PCIe, DDR, and related protocols.