Lead FPGA/ASIC Verification Engineer — SystemVerilog/UVM

Lattice Malaysia; Malaysia; On-site; MYR 180,000 - 260,000; Full time

Job summary

Lattice Semiconductor Malaysia is seeking an experienced verification engineer to lead FPGA/ASIC verification across complex IPs and SoCs. You will design scalable SystemVerilog/UVM environments, drive coverage goals, and mentor junior engineers in a fast-paced team focused on innovation and quality.

Responsibilities include sign-off activities, debugging across RTL to system-level tests, and close collaboration with design, firmware, and validation teams to ensure successful silicon tape-out.

Qualifications

• 5+ years of ASIC/FPGA functional verification experience.
• Strong SystemVerilog and UVM expertise.
• Experience building verification environments with drivers, monitors, scoreboards, and coverage.

Responsibilities

• Lead verification of FPGA/ASIC IPs, subsystems, and SoC features from spec to tape-out.
• Develop verification strategies, test plans, and closure criteria.
• Architect and build SystemVerilog/UVM environments, checkers, assertions, and coverage models.
• Drive constrained-random and directed verification for coverage goals.
• Debug design/testbench/simulation across RTL, GLS, low-power, and system-level scopes.
• Collaborate with architects, design, firmware, and validation teams.
• Lead verification sign-off: coverage closure, regression analysis, risk assessment.
• Mentor junior verification engineers and improve reusable infrastructure.
• Support silicon bring-up and root-cause analysis when required.

Skills

SystemVerilog

UVM

Python

Perl

Shell scripting

Debugging

Education

Bachelor's or Master's in Electrical/Electronic Engineering or Computer Engineering

Tools

Simulators

Verification tools

Job description

Lattice Semiconductor Malaysia is seeking an experienced verification engineer to lead FPGA/ASIC verification across complex IPs and SoCs. You will design scalable SystemVerilog/UVM environments, drive coverage goals, and mentor junior engineers in a fast-paced team focused on innovation and quality.

Responsibilities include sign-off activities, debugging across RTL to system-level tests, and close collaboration with design, firmware, and validation teams to ensure successful silicon tape-out.