Senior Physical Design Engineer

UST; Penang; On-site; MYR 120,000 - 240,000; Full time

Job summary

UST is seeking a seasoned Physical Design Engineer to own the complete flow from synthesis to tape-out for high-speed interfaces in advanced FinFET processes. You will perform full-custom analog/mixed-signal layout, Place & Route, STA analysis, and physical verification in a collaborative team.

You will optimize floorplanning, power grid, EMIR/noise handling, DFM/DFR, and block-level LEF/DEF integration, while mentoring younger engineers and driving design closures across 16nm/14nm technology

Qualifications

• Experienced in synthesis, Place & Route, timing closure, PV, PI, PPA improvement with major EDA tools.
• Implementation of multimillion gate SoC designs in cutting edge process technologies (16nm,14nm & below).
• Good understanding of timing concepts and ECOs to fix timing, noise, and EMIR violations.

Responsibilities

• Lead full-custom analog and mixed-signal layout for high-speed interfaces (SerDes, PHY) in deep submicron FinFETs.
• Deliver P&R data and ensure timing, EMI/EMIR compliance, and verification throughout the flow.

Skills

Synthesis

Place & Route

Timing closure

PV/PI/PPA optimization

Floor planning

Tcl/Perl/Python

Tools

Cadence

Synopsys

Mentor Graphics

Calibre DRC/LVS

Totem EM/IR

Job description

Responsible for all aspects of Physical design (Place & Route, STA analysis, PI/SI analysis, physical verification, DFR design and verification, DFM design and verification, physical design data delivery.), Full custom and its implementation in a team environment performing full-custom analog and mixed-signal layout of next generation high-speed interfaces and signal integrity systems (aka SerDes, PHY) in deep submicron FinFET technologies.

Job Requirements:

• Experienced in synthesis, Place & Route, timing closure, PV, PI, PPA improvement. etc and major EDA tools including Cadence, Synopsys, and Mentor tools.
• Implementation of multimillion gate SoC designs in cutting edge process technologies (16nm,14nm & below). Experience in Finfet technologies is a must.
• Expertise in floor planning including power grid design to meet EMIR specifications.
• Good understanding of timing concepts, Experience in Generating and Implementing ECOs to fix timing, noise, and EMIR violations.
• Experience in Tcl/Perl/Shell/Python programming, Mentor Calibre DRC/LVS/PERC, and Apache Totem EM & IR analysis is a plus.
• Familiar with mixed signal layout matching techniques, such as interdigitation, common centroid and dummies for matching, bypass capacitor design and optimization, power supply bus construction using star connections, critical route shielding, triple well layout, ESD device and cell layout, and guard ring layout methods.
• Knowledge of low-power UPF flows. Ability to create LEF and DEF of analog/custom blocks, define the pins ports for the block, integrate them into the P&R database, and maintain the hierarchy for extraction and verification. Need to be able to merge and integrate the database into the Cadence Virtuoso database.
• Good understanding of advanced semiconductor technology process and device physics. Strong in digital logic design, CMOS & strong analytical ability.
• Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment