Senior Physical Design Engineer— High-Speed SoC Layout

UST; Bayan Lepas; On-site; MYR 180,000 - 280,000; Full time

Job summary

UST is seeking a senior Physical Design engineer to own end-to-end analog/mixed-signal layout for next-gen high-speed interfaces in FinFET tech. You will drive synthesis, P&R, and timing closure, and mentor junior designers in a collaborative team environment.

Your role emphasizes floorplanning, power-grid design, ECO creation, and USE of Cadence/Synopsys/Mentor tools to deliver high-quality tapeouts. A strong background in UPF flows and LEF/DEF creation is required.

Qualifications

• Synthesis, Place & Route, timing closure, PV, PI, PPA improvement using major EDA tools.
• Implementation of multimillion gate SoC designs in cutting-edge process technologies (16nm, 14nm & below). FinFET experience required.
• Expertise in floor planning including power grid design to meet EMIR specifications.
• Strong timing concepts knowledge; ability to generate and implement ECOs to fix timing, noise, and EMIR violations.
• Proficiency in Tcl/Perl/Shell/Python scripting for automation and flows.
• Familiar with mixed-signal layout matching techniques (interdigitation, centroid, dummies).
• Knowledge of UPF flows; create LEF/DEF for analog blocks and integrate into P&R database.
• Understanding of advanced semiconductor process and device physics; strong digital logic and analytical skills.

Responsibilities

• Own all aspects of physical design for high-speed SerDes and PHY blocks in deep submicron FinFETs.
• Collaborate in a team to deliver full-custom analog/mixed-signal layouts and data delivery.
• Execute floorplanning, power distribution, and routing to meet performance and reliability targets.

Skills

Place & Route

Synthesis

Timing closure

PV/PI/Power integrity

PPA improvement

Automation scripting

LEF/DEF for analog blocks

UPF flows

Mixed-signal layout

CMOS/FinFET tech

Tools

Cadence

Synopsys

Mentor Graphics

Calibre DRC/LVS/PERC

Apache Totem EM & IR analysis

Cadence Virtuoso

Job description

UST is seeking a senior Physical Design engineer to own end-to-end analog/mixed-signal layout for next-gen high-speed interfaces in FinFET tech. You will drive synthesis, P&R, and timing closure, and mentor junior designers in a collaborative team environment.

Your role emphasizes floorplanning, power-grid design, ECO creation, and USE of Cadence/Synopsys/Mentor tools to deliver high-quality tapeouts. A strong background in UPF flows and LEF/DEF creation is required.