Junior PD Engineer: Analog/Mixed-Signal Layout (FinFET)

UST Global (M) Sdn Bhd; Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

UST Global (M) Sdn Bhd is seeking a hardware design professional to lead physical design for high-speed SerDes and PHY in deep submicron FinFET technologies. You will perform full-custom analog and mixed-signal layout in a team environment and own Place & Route, STA analysis, PI/SI analysis, and physical verification.

Responsibilities include LEF/DEF creation for analog blocks, P&R database integration, and ECO-driven timing/noise fixes.

Qualifications

• Bachelor-level engineering degree required.
• Minimum 2 years of relevant physical design experience.
• Experience with 16nm/14nm FinFET or below processes.
• Strong knowledge of analog/mixed-signal layout and verification.
• Proficiency with EDA tools: Cadence, Synopsys, Mentor; Adaptation to P&R workflows.

Responsibilities

• Lead full-custom analog/mixed-signal layout for SerDes/PHY blocks.
• Perform Place & Route, STA, PI/SI analysis, and physical verification.
• Create LEF/DEF for analog blocks and maintain P&R database hierarchy.
• Merge and integrate design data into Cadence Virtuoso ecosystem and support ECO-driven fixes.

Skills

Synthesis & P&R

Timing closure

ECO generation

Scripting (Tcl/Perl/Python)

Analog/mixed-signal layout

Power grid design & EMIR

Education

Bachelor of Engineering or ME/M.Tech

Tools

Cadence

Synopsys

Mentor Graphics

Calibre

Job description

UST Global (M) Sdn Bhd is seeking a hardware design professional to lead physical design for high-speed SerDes and PHY in deep submicron FinFET technologies. You will perform full-custom analog and mixed-signal layout in a team environment and own Place & Route, STA analysis, PI/SI analysis, and physical verification.

Responsibilities include LEF/DEF creation for analog blocks, P&R database integration, and ECO-driven timing/noise fixes.