Senior Physical Design Engineer

Altera; George Town; On-site; MYR 120,000 - 180,000; Full time

Job summary

Altera in Penang, Malaysia, is seeking a seasoned Physical Design Engineer to drive RTL-to-GDS implementation for complex IP and SoC designs. You will oversee synthesis, place-and-route, clock tree synthesis, floorplanning, STA, power and noise analysis, and signoff verification across multi-domain designs.

Ideal candidates have 5+ years in physical design, experience with deep submicron nodes, and strong scripting plus HDL skills, with mentorship capability and a collaborative, cross-functional

Qualifications

• Bachelor's degree in computer engineering or electronic engineering or related field.
• 5+ years of experience in physical design; multiple tape-out experience in deep submicron nodes; extensive knowledge of physical design flow and EDA tools; signoff flows (STA/LEC/ERC/DRC).
• Proficient in Perl, TCL, Python; HDL: VHDL/Verilog.
• Experience mentoring junior team members; strong initiative and analytical skills; multitasking in diverse teams.

Responsibilities

• Perform physical design implementation of RTL to GDS to prepare manufacturing data.
• Conduct synthesis, place-and-route, clock tree synthesis, floorplanning, STA, power/clock distribution, reliability, and noise analysis.
• Conduct verification and signoff: formal equivalence verification, STA, reliability verification, power integrity, layout verification, ERC, DRC.
• Analyze results and recommend fixes; optimize design for power, frequency, and area; contribute to design methodology improvements.

Skills

Physical design

Scripting (Perl TCL Python)

HDL VHDL Verilog

Mentoring

Problem solving

Education

Bachelor's degree in computer engineering or electronic engineering

Master's degree in computer/electronic engineering (preferred)

Tools

EDA tools

Job description

Job Description

Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. Optimizes design to improve product-level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

Education and Qualifications

• Bachelor's degree in computer engineering, electronic Engineering or related field.
• Minimum Qualifications 5+ years of relevant experience in the following areas: Have multiple tape-out experience in deep submicron process nodes in depth, extensive knowledge and hands-on experience in physical design flow and relevant EDA tools in depth, extensive knowledge and hands-on experience in physical design signoff flow, such as STA flow, LEC flow, ERC flow and DRC flow. Hands-on expertise with scripting languages such as Perl, TCL, Python and knowledge of hardware description languages of VHDL and Verilog. Experience of mentoring junior team members and charting their development for success. Possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment.

Preferred Requirements

• Master's degree in computer engineering, Electronic Engineering or related field.
• 5+ years of experience in the following areas: Physical design involving multiple clock domains and clock, power management. Low power design, tools and methodologies. Power intent UPF specifications.

Job Type

Regular

Shift: Shift 1 (Malaysia)

Location

Primary Location: Penang 15, Penang, Malaysia

Additional Locations:

Equal Opportunity

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

About Altera

Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.