Junior/Senior Physical Design Engineer

UST Global (M) Sdn Bhd; Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

UST Global (M) Sdn Bhd is seeking a hardware design professional to lead physical design for high-speed SerDes and PHY in deep submicron FinFET technologies. You will perform full-custom analog and mixed-signal layout in a team environment and own Place & Route, STA analysis, PI/SI analysis, and physical verification.

Responsibilities include LEF/DEF creation for analog blocks, P&R database integration, and ECO-driven timing/noise fixes.

Qualifications

• Bachelor-level engineering degree required.
• Minimum 2 years of relevant physical design experience.
• Experience with 16nm/14nm FinFET or below processes.
• Strong knowledge of analog/mixed-signal layout and verification.
• Proficiency with EDA tools: Cadence, Synopsys, Mentor; Adaptation to P&R workflows.

Responsibilities

• Lead full-custom analog/mixed-signal layout for SerDes/PHY blocks.
• Perform Place & Route, STA, PI/SI analysis, and physical verification.
• Create LEF/DEF for analog blocks and maintain P&R database hierarchy.
• Merge and integrate design data into Cadence Virtuoso ecosystem and support ECO-driven fixes.

Skills

Synthesis & P&R

Timing closure

ECO generation

Scripting (Tcl/Perl/Python)

Analog/mixed-signal layout

Power grid design & EMIR

Education

Bachelor of Engineering or ME/M.Tech

Tools

Cadence

Synopsys

Mentor Graphics

Calibre

Job description

Responsible for all aspects of Physical design (Place & Route, STA analysis, PI/SI analysis, physical verification, DFR design and verification, DFM design and verification, physical design data delivery.), Full custom and its implementation in a team environment performing full-custom analog and mixed-signal layout of next generation high-speed interfaces and signal integrity systems (aka SerDes, PHY) in deep submicron FinFET technologies.

Job Requirements:

Experienced in synthesis, Place & Route, timing closure, PV, PI, PPA improvement. etc and major EDA tools including Cadence, Synopsys, and Mentor tools.

Implementation of multimillion gate SoC designs in cutting edge process technologies (16nm,14nm & below). Experience in Finfet technologies is a must.

Expertise in floor planning including power grid design to meet EMIR specifications.

Good understanding of timing concepts, Experience in Generating and Implementing ECOs to fix timing, noise, and EMIR violations.

Experience in Tcl/Perl/Shell/Python programming, Mentor Calibre DRC/LVS/PERC, and Apache Totem EM & IR analysis is a plus.

Familiar with mixed signal layout matching techniques, such as interdigitation, common centroid and dummies for matching, bypass capacitor design and optimization, power supply bus construction using star connections, critical route shielding, triple well layout, ESD device and cell layout, and guard ring layout methods.

Knowledge of low-power UPF flows. Ability to create LEF and DEF of analog/custom blocks, define the pins ports for the block, integrate them into the P&R database, and maintain the hierarchy for extraction and verification. Need to be able to merge and integrate the database into the Cadence Virtuoso database.

Good understanding of advanced semiconductor technology process and device physics. Strong in digital logic design, CMOS & strong analytical ability.

Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment

At least 2 years of relevant experience

Bachelor of Engineering or ME/M.Tech