Physical Design Engineer

Russell Tobin; Bayan Lepas; On-site; MYR 180,000 - 240,000; Full time

Job summary

Russell Tobin is seeking an experienced ASIC physical design engineer in Malaysia (Penang/Bayan Lepas) to lead PnR activities from RTL to GDSII. You will develop flows using Perl/TCL, drive floor planning, CTS, routing, and sign-off while solving lower-node challenges to meet performance, area, and power targets.

Ideal candidates have hands-on experience with Synthesis, Floor planning, Clock tree synthesis, Parasitic extraction, STA, and physical verification, plus strong communication skills

Qualifications

• Experience in ASIC PnR (Top/Block level) from RTL to GDSII.
• Hands-on experience with synthesis, floor planning, placement, CTS, routing, STA, parasitic extraction, physical verification and sign-off.
• Excellent communication and presentation skills; ability to collaborate with global teams.
• Ability to drive tasks independently and mentor junior engineers.

Responsibilities

• Develop and implement flow/methodology for PnR using Perl/TCL.
• Work on lower node designs (10nm/7nm/5nm and below) with multiple customers.
• Troubleshoot and optimize physical design for performance, area, and power.

Job description

• Working on 10nm/7nm/5nm or lower nodes designs with various customers.
• Responsible to understand and develop flow/methodology using Perl/TCL programming for PnR activities (Floor planning, Placement, CTS, and Routing).
• Expertise in solving lower node technology related problems for critical designs to achieve desired performance, area, and power targets.
• Provide training and technical assistance to peers/customers.

Preferred Experience:

• Experience in Top/Block level ASIC PnR implementation (RTL to GDSII).
• Tape-out experience in lower nodes like 3nm, 5nm, 7nm, 10nm and above.
• Hands-on experience in Synthesis, Floor planning, Placement, Clock tree synthesis, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification (DRC/LVS/DFM, chip finishing) and Sign Off.
• Excellent communication and presentation skills, experience in collaborating with global teams.
• Experience in hierarchical designs and/or Low Power implementation is an advantage.
• Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics tool set.
• Must be an initiative-taker and be able to drive tasks independently and efficiently to completion.
• Ability to provide mentorship and guidance to junior engineers and be an effective team player.