Senior Physical Design Engineer - FinFET & SerDes

UST; Penang; On-site; MYR 120,000 - 240,000; Full time

Job summary

UST is seeking a seasoned Physical Design Engineer to own the complete flow from synthesis to tape-out for high-speed interfaces in advanced FinFET processes. You will perform full-custom analog/mixed-signal layout, Place & Route, STA analysis, and physical verification in a collaborative team.

You will optimize floorplanning, power grid, EMIR/noise handling, DFM/DFR, and block-level LEF/DEF integration, while mentoring younger engineers and driving design closures across 16nm/14nm technology

Qualifications

• Experienced in synthesis, Place & Route, timing closure, PV, PI, PPA improvement with major EDA tools.
• Implementation of multimillion gate SoC designs in cutting edge process technologies (16nm,14nm & below).
• Good understanding of timing concepts and ECOs to fix timing, noise, and EMIR violations.

Responsibilities

• Lead full-custom analog and mixed-signal layout for high-speed interfaces (SerDes, PHY) in deep submicron FinFETs.
• Deliver P&R data and ensure timing, EMI/EMIR compliance, and verification throughout the flow.

Skills

Synthesis

Place & Route

Timing closure

PV/PI/PPA optimization

Floor planning

Tcl/Perl/Python

Tools

Cadence

Synopsys

Mentor Graphics

Calibre DRC/LVS

Totem EM/IR

Job description

UST is seeking a seasoned Physical Design Engineer to own the complete flow from synthesis to tape-out for high-speed interfaces in advanced FinFET processes. You will perform full-custom analog/mixed-signal layout, Place & Route, STA analysis, and physical verification in a collaborative team.

You will optimize floorplanning, power grid, EMIR/noise handling, DFM/DFR, and block-level LEF/DEF integration, while mentoring younger engineers and driving design closures across 16nm/14nm technology