Physical Design Engineer

Alchip Technologies; Bayan Lepas; On-site; MYR 70,000 - 110,000; Full time

Job summary

Alchip Technologies in Penang, Bayan Lepas is seeking an experienced physical design engineer to execute gate-level netlist to GDS flow, including floor planning, place & route, and timing sign-off with full verification. You will also implement IPs, perform IR drop analysis, DFT, STA, and coordinate foundry merges.

In this role you will collaborate with the manager to meet tape-out targets, contribute to top-level chip floor plans, and work with TCL/ Perl scripting to streamline design

Qualifications

• Bachelor's or MS in EE or related field.
• Solid knowledge on digital/analog electrical; Verilog/synthesis/floorplan will be a plus.
• Experience on top level design with chip level floor plan is a plus.
• Familiar with TCL/ Perl scripting and design automation.
• Familiar with Cadence EDI, Synopsys ICC, and Mentor Calibre for physical design engineering.

Responsibilities

• Perform gate level netlist to GDS design independently including but not limited to floor planning, place & route, close tree synthesis, timing sign off and physical verification.
• Perform design IP Implementation, IR drop analysis, DFT, STA and foundry merge.
• Work with manager to achieve assigned tape out target.

Skills

Digital/Analog knowledge

Verilog

Floorplanning

Scripting (TCL/Perl)

Education

Bachelor's or MS Degree in EE

Tools

Cadence EDI

Synopsys ICC

Mentor Calibre

Job description

• Perform gate level netlist to GDS design independently including but not limited to floor planning, place & route, close tree synthesis, timing sign off and physical verification.
• Perform design IP Implementation, IR drop analysis, DFT, STA and foundry merge.
• Work with manager to achieve assigned tape out target.

Qualifications

• Bachelor or MS Degree in EE or related.
• Must has solid knowledge on digital/analog electrical; knowledge on verilog/ synthesis/ floorplan will be a plus.
• Experience of working on top level design with chip level floor plan is a plus.
• Familiar with Cadence EDI, Synopsys ICC design flow and Mentor Calibre for physical design engineer.
• Familiar with TCL/ Perl scripting and design automation.