Physical Design Engineer

Pride Global; Seberang Perai; On-site; MYR 123,000 - 201,000; Full time

Job summary

Pride Global in Malaysia is seeking a Physical Design Engineer with 4+ years ASIC experience to drive the Netlist-to-GDSII flow for advanced nodes (7nm/5nm/3nm). This onsite role offers challenging floorplanning, power planning, placement, CTS, routing and timing closure to deliver high-performance ASICs.

You will collaborate with cross-functional teams, fix setup/hold, IR drop and SI issues, perform DRC/LVS/ERC checks, and develop Tcl/Python scripts to automate flows using Synopsys ICC2,

Qualifications

• Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering.
• 4+ years of ASIC Physical Design experience.
• Strong expertise in Netlist-to-GDSII flow, STA, CTS, and P&R.
• Hands-on experience with Synopsys (ICC2, PrimeTime) or Cadence (Innovus, Tempus).
• Proficiency in Tcl and/or Python scripting.
• Experience with advanced technology nodes (7nm/5nm/3nm) is preferred.

Responsibilities

• Perform floorplanning, power planning, placement, CTS, routing, and timing closure.
• Analyze and fix setup/hold violations, signal integrity, IR-drop, and electromigration issues.
• Execute DRC, LVS, ERC, and antenna checks to achieve signoff-quality designs.
• Develop Tcl/Perl/Python scripts to automate physical design flows.
• Collaborate with cross-functional teams to deliver high-performance, low-power ASICs.

Skills

Netlist-to-GDSII flow

STA & Timing closure

P&R (Place & Route)

DRC/LVS/ERC checks

Tcl scripting

Python scripting

ASIC Physical Design

7nm/5nm/3nm node experience

Education

Electrical/Electronics/Computer Engineering degree

Tools

ICC2

PrimeTime

Innovus

Tempus

Job description

Employment type : Open to Perm & Contract

Working arrangement : Onsite

Salary Range : 4 – 6 Years (11-12k), 6 – 8 Years (13-15k), 8 – 10 Years (16-18k)

We are seeking a Physical Design Engineer with 4+ years of ASIC physical design experience to drive the complete Netlist-to-GDSII implementation flow for advanced technology nodes (7nm/5nm/3nm).

Key Responsibilities:

• Perform floorplanning, power planning, placement, CTS, routing, and timing closure.
• Analyze and fix setup/hold violations, signal integrity, IR-drop, and electromigration issues.
• Execute DRC, LVS, ERC, and antenna checks to achieve signoff-quality designs.
• Develop Tcl/Perl/Python scripts to automate physical design flows.
• Collaborate with cross-functional teams to deliver high-performance, low-power ASICs.

Requirements:

• Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering.
• 4+ years of ASIC Physical Design experience.
• Strong expertise in Netlist-to-GDSII flow, STA, CTS, and P&R.
• Hands-on experience with Synopsys (ICC2, PrimeTime) or Cadence (Innovus, Tempus).
• Proficiency in Tcl and/or Python scripting.
• Experience with advanced technology nodes (7nm/5nm/3nm) is preferred.