Physical Design Engineer

Uni Connect; Bayan Lepas; On-site; MYR 60,000 - 80,000; Full time

Job summary

A technology design company in Bayan Lepas is looking for an experienced engineer to participate in cutting-edge System-On-a-Chip (SoC) design projects. The ideal candidate possesses a Bachelor’s degree in electrical engineering and has strong understanding of digital logic and Verilog. Responsibilities include executing physical design flows and improving methodologies within aggressive schedules. Familiarity with Synopsys and Cadence EDA tools is essential. Competitive salary and growth opportunities are offered.

Qualifications

• Strong understanding of digital logic, VHDL/RTL representations, and Verilog.
• Experience with Synopsys EDA tools, including Fusion Compiler, PrimeTime.
• Hands-on experience with place‑and‑route (PnR), physical verification, timing convergence.

Responsibilities

• Participate in SoC design projects using cutting-edge technology.
• Execute complete physical design flow from RTL to GDS.
• Work as part of a team both locally and with remote teams.

Skills

Digital logic understanding

VHDL/RTL representations

Verilog proficiency

Perl programming

TCL scripting

Python for CAD automation

Education

Bachelor’s degree in electrical engineering or related discipline

Tools

Synopsys EDA tools

Cadence EDA tools

Job description

Bayan Lepas, Malaysia | Posted on 04/08/2026

Responsibilities

• You will be participating in the leading-edge System‑On‑a‑Chip (SoC) design projects using cutting‑edge process technology nodes for various client applications.
• Execute complete physical design flow from RTL to GDS (synthesis, floorplan, power grid, place and route, clock tree synthesis), participating in design/architecture reviews to track design milestones.
• Evaluate and improve physical design methodologies to handle increasingly complex SoC/IP designs within aggressive, market‑driven schedules.
• Actively work as part of a team both locally and with remote or multi‑site teams.
• Actively assists full chip timing constraints development, full chip Static Timing Analysis, and timing signoff for a complex, multi‑clock, multi‑voltage SoC.
• Actively assists in full chip physical verification activities including DRC and LVS convergence &

Requirements

Key Requirements:

• Minimum of Bachelor’s degree in electrical engineering, Electronics Engineering, Computer Engineering, or a related discipline.
• Strong understanding of digital logic, VHDL/RTL representations, and Verilog.
• Proficiency in Perl, TCL, and Python for CAD flow automation and optimization.
• Experience with Synopsys EDA tools, including Fusion Compiler, PrimeTime, IC Validator, and VC
• Successful completion and/or tapeouts on advanced FinFET technology nodes (16nm, 12nm, 7nm,
• Hands‑on experience with place‑and‑route (PnR) including floorplanning & clock tree synthesis (CTS), physical verification, timing convergence and IR drop analysis.
• Experience in automated design flows and automated synthesis.

Additional Skills:

• Hands‑on experience with full‑chip or sub‑chip Static Timing Analysis, timing constraint development, and timing closure.
• Experience with advanced sign‑off activities, including Lint, CDC, LEC, scan, and ECO flows.
• Experience in top‑level physical implementation.
• Experience with Cadence EDA tools, including Innovus, Tempus, Virtuoso, and Conformal.
• Experience with power analysis and power optimization techniques.