Senior/Lead Mask Design Engineer

UST; Seberang Perai; On-site; MYR 120,000 - 180,000; Full time

Job summary

UST in Malaysia seeks an experienced IC layout engineer to execute high density Si layout designs for EMIB, interposer and test chips. You will create custom IC layouts to specification and run comprehensive verification including DRC/LVS and reliability checks.

The role requires 7+ years of IC layout experience, proficiency with Cadence Virtuoso, and strong problem-solving skills to troubleshoot complex layout issues and optimize flows.

Qualifications

• Bachelor's degree in Electronics Engineering or related field.
• 7+ years of experience in IC layout/design.
• Experience with advanced packaging elements and Si manufacturing nodes.
• Proficient with Cadence Virtuoso.

Responsibilities

• Execute high density Si layout designs across advanced packaging elements (EMIB, Interposer, Test Chips).
• Create custom IC layouts to specification and run full verification (DRC, LVS, reliability checks).
• Analyze input bumps/floorplans, layout structures, signal routing, power grid, and perform verification.

Skills

Si layout design

Layout verification

DRC/LVS

Problem solving

Project coordination

Education

Bachelor's Degree in Electronics Engineering

Tools

Cadence Virtuoso

Design verification tools

Job description

• Executing high density Si layout designs across advanced packaging elements (EMIB, Interposer, Test Chips and more).
• Creates custom layouts of Integrated Circuits (EMIB, Si Interposer, Full loop/Short loop Test Chips etc,) for a given specification and runs complete set of design verification tools for process design rules, electron migration, voltage drop (IR), ESD, and other reliability checks on the layouts. Creates accurate designs that meet project needs, applying understanding of design manuals, established processes, layout elements, and basic electronic principles.
• Designs and analyzes input bumps/floorplans, layout structures, signal routing, differential pair checks, power grid, DRC, LVS and performs all required verification on the layout blocks/top level.
• Troubleshoots a wide variety of issues up to and including layouts and tool/flow/methodology used in Si layout design.
• Fluent in Si custom layout design tools - Cadence Virtuoso Platform Works with project stakeholders to align on projects, schedule, provide updates, and resolve issues.
• Good domain understanding in advanced Si Manufacturing nodes and advanced packaging structures Qualifications:
• Possess a Bachelors Degree in Electronics Engineering or relevant disciplines with 7+ years of experience in the related field