Senior Analog Custom Layout Engineer

4ASICS TECHNOLOGY SDN BHD; Penang; Hybrid; MYR 120,000 - 220,000; Full time

Benefits offered by this job

hybrid working mode

contractual bonus

13th-month salary

attractive benefits, incentives andBon

EV incentive

health and fitness benefit

retention incentive

performance bonus

attendance allowance

broadband allowance

business travel allowance

medical and hospitalization coverage

team bonding activities

Job summary

4ASICS Technology Sdn Bhd in Penang is seeking a Senior Analog Custom Layout Engineer to lead full-custom analog, mixed-signal and RF layouts on FinFET projects. You will own layout implementation, floorplanning, device matching, and ensure DRC/LVS/ERC closures, collaborating with circuit designers and customers to deliver robust, manufacturable layouts with high yield.

Fluent English required. Hybrid working model with occasional travel to support international customers and post-layout

Qualifications

• Bachelor's or Master's degree in Electrical Engineering or related discipline.
• Minimum three years of hands-on analog custom layout experience, with FinFET exposure.
• Proven ability to independently execute complex analog/mixed-signal layouts with limited supervision.
• Strong experience in transistor-level layout from scratch for FinFET devices.
• Experience with planar CMOS layout is beneficial.
• Good English communication with international customers.

Responsibilities

• Independently develop full-custom analog, mixed-signal and RF layouts from schematic to tapeout.
• Own or lead layout implementation on TSMC FinFET technologies with planning and verification.
• Contribute to planar CMOS projects when required.
• Perform floorplanning, device placement, routing, power distribution and layout finishing.
• Apply advanced layout techniques (centroid, interdigitation, shielding, guard rings).
• Run and close DRC, LVS, ERC, ANT, DFM, PEX and EM/IR checks as required.
• Collaborate with circuit designers to resolve issues and support post-layout optimization.

Skills

Analog layout

RF layout

FinFET technology

Planar CMOS

Floorplanning

Layout verification

Education

Bachelor's in Electrical Engineering

Master's in Electrical Engineering

Tools

EDA tools

PCell design

Job description

Established in 2016, we have provided top-notch Analog, Mixed-Signal & RF Layout Design solutions for various industries, including RF, mobile, medical, audio, IOT, and 5G. Using cutting-edge sub-micron CMOS & FinFET technology and industrial standard EDA tools, our team delivers exceptional services to our clients.

Our workflow is guided by an ISO 9001-certified quality management system. Our customers value the quality, efficiency, flexibility and the commitment we bring, and we are also proud to be a Great Place to Work–certified organization, reflecting the strength and stability of our team.

In line with our business growth, we are looking for passionate and energetic experienced Senior Analog Custom Layout Engineer to join our big family. This position is primarily focused on advanced-node TSMC FinFET projects, while also requiring the flexibility to support planar CMOS work when needed.

What do we need you to do?

Independently develop full-custom analog, mixed-signal and RF layouts from schematic and floorplan through tapeout.

Own or lead layout implementation on TSMC FinFET technologies, including project planning, technical execution and verification closure.

Contribute to planar CMOS projects when required, applying sound analog layout fundamentals across different process technologies.

Perform floorplanning, device placement, matching, routing, power distribution, layout finishing and design optimization.

Apply advanced layout techniques such as common-centroid placement, interdigitation, symmetry, shielding, guard rings, device isolation and layout-dependent-effect-aware implementation.

Optimize layouts for matching, parasitics, performance, area, density, current flow, reliability, manufacturability and yield.

Run, debug and close physical verification checks, including DRC, LVS, ERC, ANT, DFM, PEX and EM/IR, as required by the project flow.

Collaborate directly with circuit designers and customers to resolve layout-related issues and support post-layout optimization.

Communicate progress, technical risks, dependencies and proposed solutions clearly to internal and customer stakeholders.

Conduct layout reviews, support methodology improvement and mentor less-experienced engineers when required.

To succeed in this role, we will need you to have:

Bachelor's or Master's degree in Electrical Engineering, Electronic Engineering, Microelectronics or a related discipline.

Minimum three years of hands-on analog custom layout experience, with a substantial part of that experience in FinFET technologies.

Proven ability to independently execute complex analog or mixed-signal layout work with limited supervision.

Strong practical experience in transistor level (draw from scratch from pcell and not standard cell) for TSMC FinFET custom layout, preferably on one or more of N16/N12, N7/N6, N5/N4 or N3 process families.

Working experience in planar CMOS layout.

Solid understanding of device matching, process variation, parasitic effects, signal integrity, reliability and layout-dependent effects.

Proven ability to perform physical verification and resolve DRC, LVS and related closure issues.

Ability to interpret schematics and translate circuit requirements into robust, manufacturable physical layouts.

Good written and spoken English, with the ability to work effectively with international customers and distributed teams.

Ability to manage priorities, identify technical risks and deliver quality results within agreed project timelines.

Hands-on custom layout experience in transistor level (draw from scratch from pcell and not standard cell) on TSMC N16/N12, N7/N6, N5/N4 or N3 process families.

Understanding of FinFET device construction, fin quantization, fixed or restricted grids and advanced device matching.

Experience handling advanced DRC, density constraints, restricted routing, parasitic control, current density and reliability requirements.

Ability to drive floorplanning, implementation and verification decisions independently.

Participation in a successful advanced-node tapeout is strongly preferred.

Hand-on to planar CMOS technologies, such as 180nm, 130nm, 65nm, 40nm, 28nm or 22nm.

Working knowledge of matching, symmetry, isolation, guard rings, reliability and manufacturability in planar processes.

Ability to established analog layout principles when supporting mature-node projects.

What are we providing to you in return of your skills and hard work:

• Enjoy great working flexibility when you join us as we offer hybrid working mode: work 3 days a week at office, and 2 days at home!
• We offer a contractual bonus or a 13th-month salary end of the year to express our appreciation for your commitment and trust in our organization.
• We highly appreciate your hard work and dedication to the company. As a reward, we offer attractive benefits, incentives and bonuses such as EV incentive, health and fitness benefit, retention incentive, performance bonus, etc.
• We provide miscellaneous allowances such as attendance, broadband, and business travel allowance to support your needs.
• We care about your health and wellbeing. Thus, we provide medical and hospitalization coverage when the time comes.
• Teamwork makes the dream work - We have team bonding activities from time to time to boost team spirit.

This opportunity does not come often.